公开(公告)号：US20170154893A1

公开(公告)日：2017-06-01

申请号：US15429498

申请日：2017-02-10

Applicant: Renesas Electronics Corporation

Inventor： Tamotsu OGATA

IPC: H01L27/11568 ,  H01L29/792 ,  H01L29/423 ,  H01L29/08 ,  H01L29/66 ,  G11C16/04 ,  G11C16/10 ,  H01L21/28 ,  H01L21/02 ,  H01L21/311 ,  H01L29/51 ,  G11C16/14

CPC classification number: H01L27/11568 ,  G11C16/0433 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/14 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28282 ,  H01L21/31111 ,  H01L29/0847 ,  H01L29/42344 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/792

Abstract: An improvement is achieved in the performance of a semiconductor device having a nonvolatile memory. A memory cell of the nonvolatile memory includes a control gate electrode formed over a semiconductor substrate via a first insulating film and a memory gate electrode formed over the semiconductor substrate via a second insulating film to be adjacent to the control gate electrode via the second insulating film. The second insulating film includes a third insulating film made of a silicon dioxide film, a fourth insulating film made of a silicon nitride film over the third insulating film, and a fifth insulating film over the fourth insulating film. The fifth insulating film includes a silicon oxynitride film. Between the memory gate electrode and the semiconductor substrate, respective end portions of the fourth and fifth insulating films are located closer to a side surface of the memory gate electrode than an end portion of a lower surface of the memory gate electrode. Between the memory gate electrode and the semiconductor substrate, in a region where the second insulating film is not formed, another silicon dioxide film is embedded.

公开(公告)号：US20170133394A1

公开(公告)日：2017-05-11

申请号：US15266914

申请日：2016-09-15

Applicant: Renesas Electronics Corporation

Inventor： Tamotsu OGATA

IPC: H01L27/115 ,  H01L29/423

CPC classification number: H01L27/11568 ,  G11C16/0466 ,  G11C16/30 ,  H01L27/11526 ,  H01L27/11563 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/4234 ,  H01L29/42344

Abstract: To provide a semiconductor device having improved performance. A method of manufacturing the semiconductor device includes forming, after formation of a control gate electrode and a memory gate electrode, a conductive film on an insulating film made of a high-dielectric-constant film via a metal film; patterning the conductive film and thereby forming a gate electrode including the metal film and the conductive film in a high-voltage MISFET region, while forming a metal film portion and a conductive film portion in a low-voltage MISFET region; and then, removing the conductive film portion from the low-voltage MISFET region, forming another conductive film on the metal film portion, and forming a gate electrode including the metal film portion and the another conductive film.

公开(公告)号：US20190172835A1

公开(公告)日：2019-06-06

申请号：US16264558

申请日：2019-01-31

Applicant: Renesas Electronics Corporation

Inventor： Tamotsu OGATA

IPC: H01L27/11568 ,  H01L29/66 ,  H01L21/02 ,  H01L29/51 ,  H01L27/11573 ,  H01L29/423 ,  H01L29/792 ,  H01L21/28

Abstract: A semiconductor device whose performance is improved is disclosed. In the semiconductor device, an offset spacer formed in a memory cell is formed by a laminated film of a silicon oxide film and a silicon nitride film, and the silicon oxide film is particularly formed to directly contact the sidewall of a memory gate electrode and the side end portion of a charge storage film; on the other hand, an offset spacer formed in a MISFET is formed by a silicon nitride film. Particularly in the MISFET, the silicon nitride film directly contacts both the sidewall of a gate electrode and the side end portion of a high dielectric constant film.

公开(公告)号：US20160293619A1

公开(公告)日：2016-10-06

申请号：US15043571

申请日：2016-02-14

Applicant: Renesas Electronics Corporation

Inventor： Tamotsu OGATA

IPC: H01L27/115 ,  H01L29/792 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66 ,  H01L29/51 ,  H01L29/423

CPC classification number: H01L27/11568 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28282 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/792

Abstract: A semiconductor device whose performance is improved is disclosed. In the semiconductor device, an offset spacer formed in a memory cell is formed by a laminated film of a silicon oxide film and a silicon nitride film, and the silicon oxide film is particularly formed to directly contact the sidewall of a memory gate electrode and the side end portion of a charge storage film; on the other hand, an offset spacer formed in a MISFET is formed by a silicon nitride film. Particularly in the MISFET, the silicon nitride film directly contacts both the sidewall of a gate electrode and the side end portion of a high dielectric constant film.

Abstract translation: 公开了一种提高性能的半导体器件。 在半导体器件中，形成在存储单元中的偏移间隔物由氧化硅膜和氮化硅膜的层叠膜形成，并且氧化硅膜特别形成为直接接触存储栅电极的侧壁和 电荷存储膜的侧端部; 另一方面，通过氮化硅膜形成在MISFET中形成的偏移间隔物。 特别是在MISFET中，氮化硅膜直接接触栅电极的侧壁和高介电常数膜的侧端部。

公开(公告)号：US20140147982A1

公开(公告)日：2014-05-29

申请号：US14091247

申请日：2013-11-26

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tamotsu OGATA ,  Toshifumi IWASAKI

IPC: H01L29/66

CPC classification number: H01L29/6656 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823475 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833

Abstract: Provided is a semiconductor device with improved performance and production yield. Insulating films IL2 and IL3 are formed over a semiconductor substrate in that order to cover a gate electrode. Then, the insulating films IL3 and IL2 are etched back to form sidewall spacers including the insulating films IL2 and IL3 over sidewalls of the gate electrode. The source/drain region is formed in the semiconductor substrate by ion implantation using the gate electrode and the sidewall spacer as a mask. Then, the sidewall spacers are isotropically etched on conditions where the insulating film IL2 is less likely to be etched than the third insulating film IL3 to thereby decrease the thickness of the sidewall spacer. Thereafter, a reaction layer between the metal and the source/drain region is formed over the source/drain region.

Abstract translation: 提供了具有改进的性能和产量的半导体器件。 绝缘膜IL2和IL3以这种顺序形成在半导体衬底上以覆盖栅电极。 然后，绝缘膜IL3和IL2被回蚀以在栅电极的侧壁上形成包括绝缘膜IL2和IL3的侧壁间隔物。 源极/漏极区域通过使用栅电极和侧壁间隔物作为掩模的离子注入形成在半导体衬底中。 然后，在绝缘膜IL2比第三绝缘膜IL3不太可能被蚀刻的条件下，侧壁间隔物被各向同性蚀刻，从而减小侧壁间隔物的厚度。 此后，在源极/漏极区域上形成金属和源极/漏极区域之间的反应层。

公开(公告)号：US20200098775A1

公开(公告)日：2020-03-26

申请号：US16695508

申请日：2019-11-26

Applicant: Renesas Electronics Corporation

Inventor： Tamotsu OGATA

IPC: H01L27/11568 ,  H01L29/423 ,  H01L27/11573 ,  H01L23/535

Abstract: A semiconductor device having a nonvolatile memory cell arranged in a p-type well (active region) PW1 in a memory cell region 1A in a semiconductor substrate 1 and an MISFET arranged in a p-type well PW2 (active region) or an n-type well (active region) in a peripheral circuit region 2A is constructed as follows. The surface of an element isolation region STI1 surrounding the p-type well PW1 is set lower than the surface of an element isolation region STI2 surrounding the p-type well PW2 or the n-type well (H1

公开(公告)号：US20190273057A1

公开(公告)日：2019-09-05

申请号：US16278959

申请日：2019-02-19

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tamotsu OGATA

IPC: H01L23/00

Abstract: To provide a semiconductor device that prevents a surface of a bonding pad from being made rough and can also reduce dimensions of the bonding pad, a semiconductor device according to an embodiment includes a bonding pad containing aluminum, a titanium nitride film, a passivation film, and a sidewall protection film including a first layer and a second layer. An opening is provided in the titanium nitride film and the passivation film. The opening includes a sidewall and exposes the bonding pad therethrough. The first layer of the sidewall protection film covers at least the titanium nitride film over the sidewall, and the second layer covers the first layer. A material forming the first layer and a material forming the second layer are different from each other in an etching rate in etching under the same condition.

公开(公告)号：US20190172837A1

公开(公告)日：2019-06-06

申请号：US16269797

申请日：2019-02-07

Applicant: Renesas Electronics Corporation

Inventor： Tomohiro YAMASHITA ,  Tamotsu OGATA ,  Masamichi FUJITO ,  Tomoya SAITO

IPC: H01L27/11573 ,  H01L27/11568 ,  H01L21/8238 ,  H01L49/02 ,  H01L21/28 ,  H01L29/423 ,  H01L27/1157 ,  H01L29/94 ,  H01L29/792 ,  H01L29/78 ,  H01L27/06 ,  H01L29/66

CPC classification number: H01L27/11573 ,  H01L21/823821 ,  H01L27/0629 ,  H01L27/11568 ,  H01L27/1157 ,  H01L28/87 ,  H01L28/90 ,  H01L28/91 ,  H01L29/40114 ,  H01L29/41791 ,  H01L29/42344 ,  H01L29/66181 ,  H01L29/66795 ,  H01L29/66833 ,  H01L29/7853 ,  H01L29/7855 ,  H01L29/792 ,  H01L29/94

Abstract: To downsize a semiconductor device that includes a non-volatile memory and a capacitive element on a semiconductor substrate. In a capacitive element region of a main surface of a semiconductor substrate, fins protruding from the main surface are arranged along the Y direction while extending in the X direction. In the capacitive element region of the main surface of the semiconductor substrate, capacitor electrodes of the capacitive elements are alternately arranged along the X direction while intersecting the fins. The fins are formed in a formation step of other fins which are arranged in a memory cell array of the non-volatile memory of the semiconductor substrate. One capacitor electrode is formed in a formation step of a control gate electrode of the non-volatile memory. Another capacitor electrode is formed in a formation step of a memory gate electrode of the non-volatile memory.

公开(公告)号：US20180090508A1

公开(公告)日：2018-03-29

申请号：US15658759

申请日：2017-07-25

Applicant: Renesas Electronics Corporation

Inventor： Tamotsu OGATA

IPC: H01L27/11568 ,  H01L23/535 ,  H01L27/11573 ,  H01L29/423

CPC classification number: H01L27/11568 ,  H01L23/535 ,  H01L27/11573 ,  H01L29/42344

Abstract: A semiconductor device having a nonvolatile memory cell arranged in a p-type well (active region) PW1 in a memory cell region 1A in a semiconductor substrate 1 and an MISFET arranged in a p-type well PW2 (active region) or an n-type well (active region) in a peripheral circuit region 2A is constructed as follows. The surface of an element isolation region STI1 surrounding the p-type well PW1 is set lower than the surface of an element isolation region STI2 surrounding the p-type well PW2 or the n-type well (H1

公开(公告)号：US20170352676A1

公开(公告)日：2017-12-07

申请号：US15582923

申请日：2017-05-01

Applicant: Renesas Electronics Corporation

Inventor： Tamotsu OGATA

IPC: H01L27/11568 ,  H01L29/66 ,  H01L21/265 ,  H01L21/28 ,  H01L29/792 ,  H01L29/78

Abstract: An improvement is achieved in the performance of a semiconductor device having a nonvolatile memory. A first memory cell includes a first control gate electrode and a first memory gate electrode which are formed over a semiconductor substrate to be adjacent to each other. A second memory cell includes a second control gate electrode and a second memory gate electrode which are formed over the semiconductor substrate to be adjacent to each other. A width of a sidewall spacer formed on a side of the second memory gate electrode opposite to a side thereof where the second memory gate electrode is adjacent to the second control gate electrode is smaller than a width of another sidewall spacer formed on a side of the first memory gate electrode opposite to a side thereof where the first memory gate electrode is adjacent to the first control gate electrode. A threshold voltage of a first memory transistor including the first memory gate electrode in a neutral state is different a threshold voltage of a second memory transistor including the second memory gate electrode in the neutral state.