公开(公告)号：US09183914B2

公开(公告)日：2015-11-10

申请号：US13682578

申请日：2012-11-20

Applicant: Renesas Electronics Corporation

Inventor： Fukuo Owada

IPC: G11C11/00 ,  G11C5/14 ,  G11C11/21 ,  G11C14/00

CPC classification number: G11C11/21 ,  G11C14/009

Abstract: A first ReRAM unit having a resistance change layer is provided between a first access transistor configuring the SRAM and a first bit line, and a second ReRAM unit having a resistance change layer is provided between a second access transistor and a second bit line. When a low potential (L=0V) is held at a first storage node and a high potential (H=1.5V) is held at a second storage node at the end of a normal operation period of the SRAM, the first ReRAM unit is set to ON state (ON), and the second ReRAM unit is set to OFF state (OFF); accordingly, the retained data of the SRAM is written in to the ReRAM units. When the SRAM returns to the normal operation again, data corresponding to the storage nodes are written back and the ReRAM units are both set to ON state (reset).

Abstract translation: 具有电阻变化层的第一ReRAM单元设置在构成SRAM的第一存取晶体管和第一位线之间，并且具有电阻变化层的第二ReRAM单元设置在第二存取晶体管和第二位线之间。 当在第一存储节点处保持低电位（L = 0V）并且在SRAM的正常工作周期结束时在第二存储节点处保持高电位（H = 1.5V）时，第一ReRAM单元是 设置为ON状态（ON），第二个ReRAM单元设置为OFF状态（OFF）; 因此，SRAM的保留数据被写入ReRAM单元。 当SRAM再次返回到正常操作时，对应于存储节点的数据被写回，并且ReRAM单元都被设置为ON状态（复位）。

公开(公告)号：US09947679B2

公开(公告)日：2018-04-17

申请号：US14860700

申请日：2015-09-21

Applicant: Renesas Electronics Corporation

Inventor： Fukuo Owada ,  Masaaki Shinohara ,  Takahiro Maruyama

IPC: H01L27/115 ,  H01L27/11546 ,  H01L27/11529

CPC classification number: H01L27/11546 ,  H01L27/11529

Abstract: An improvement is achieved in the performance of a semiconductor device. Over a first insulating film formed over a main surface of a semiconductor substrate located in a memory formation region and having an internal charge storage portion and over a second insulating film formed over the main surface of the semiconductor substrate located in a main circuit formation region, a conductive film is formed. Then, in the memory formation region, the conductive film and the first insulating film are patterned to form a first gate electrode and a first gate insulating film while, in the main circuit formation region, the conductive film and the second insulating film are left. Then, in the main circuit formation region, the conductive film and the second insulating film are patterned to form a second gate electrode and a second gate insulating film.

公开(公告)号：US09293604B2

公开(公告)日：2016-03-22

申请号：US14538803

申请日：2014-11-11

Applicant: Renesas Electronics Corporation

Inventor： Fukuo Owada

IPC: H01L21/336 ,  H01L29/792 ,  H01L29/66 ,  H01L29/51 ,  H01L21/28 ,  H01L21/02 ,  H01L29/423

CPC classification number: H01L29/792 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02238 ,  H01L21/02326 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/511 ,  H01L29/518 ,  H01L29/66833

Abstract: To provide a semiconductor device with nonvolatile memory, having improved performance.A memory cell has control and memory gate electrodes on a semiconductor substrate via an insulating film and another insulating film having first, second, and third films stacked one after another in order of mention, respectively. The memory and control gate electrodes are adjacent to each other via the stacked insulating film. The second insulating film has a charge accumulation function. The first and third insulating films each have a band gap greater than that of the second insulating film. An inner angle of the second insulating film between a portion extending between the semiconductor substrate and the memory gate electrode and a portion extending between the control gate electrode and the memory gate electrode is ≧90°. An inner angle of the corner portion between the lower surface and the side surface of the memory gate electrode is

Abstract translation: 为了提供具有非易失性存储器的半导体器件，具有改进的性能。 存储单元经由绝缘膜在半导体衬底上具有控制和存储栅电极，另一绝缘膜分别具有依次层叠的第一，第二和第三膜。 存储器和控制栅电极通过堆叠的绝缘膜彼此相邻。 第二绝缘膜具有电荷累积功能。 第一和第三绝缘膜各自具有大于第二绝缘膜的带隙。 在半导体衬底和存储栅电极之间延伸的部分和在控制栅电极和存储栅电极之间延伸的部分之间的第二绝缘膜的内角为≥90°。 存储栅电极的下表面和侧表面之间的角部的内角<90°。

公开(公告)号：US09508554B2

公开(公告)日：2016-11-29

申请号：US14869988

申请日：2015-09-29

Applicant: Renesas Electronics Corporation

Inventor： Kazuharu Yamabe ,  Shinichiro Abe ,  Shoji Yoshida ,  Hideaki Yamakoshi ,  Toshio Kudo ,  Seiji Muranaka ,  Fukuo Owada ,  Daisuke Okada

IPC: H01L21/4763 ,  H01L21/28 ,  H01L29/66 ,  H01L29/792

CPC classification number: H01L21/28282 ,  H01L21/28194 ,  H01L29/66833 ,  H01L29/792

Abstract: To provide a semiconductor device having improved performance while improving the throughput in the manufacturing steps of the semiconductor device. An insulating film portion comprised of first, second, third, fourth, and fifth insulating films is formed on a semiconductor substrate. The second insulating film is a first charge storage film and the fourth insulating film is a second charge storage film. The first charge storage film contains silicon and nitrogen; the third insulating film contains silicon and oxygen; and the second charge storage film contains silicon and nitrogen. The thickness of the third insulating film is smaller than that of the first charge storage film and the thickness of the second charge storage film is greater than that of the first charge storage film. The third insulating film is formed by treating the upper surface of the first charge storage film with a water-containing treatment liquid.

Abstract translation: 提供具有改进性能的半导体器件，同时提高半导体器件的制造步骤中的吞吐量。 在半导体衬底上形成由第一，第二，第三，第四和第五绝缘膜构成的绝缘膜部分。 第二绝缘膜是第一电荷存储膜，第四绝缘膜是第二电荷存储膜。 第一电荷储存膜含有硅和氮; 第三绝缘膜含有硅和氧; 并且第二电荷储存膜含有硅和氮。 第三绝缘膜的厚度小于第一电荷存储膜的厚度，并且第二电荷存储膜的厚度大于第一电荷存储膜的厚度。 第三绝缘膜通过用含水处理液处理第一电荷存储膜的上表面而形成。

公开(公告)号：US20160064533A1

公开(公告)日：2016-03-03

申请号：US14828046

申请日：2015-08-17

Applicant: Renesas Electronics Corporation

Inventor： Fukuo Owada

IPC: H01L29/66 ,  H01L21/266 ,  H01L21/311 ,  H01L21/265

CPC classification number: H01L27/11575 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/31111 ,  H01L21/31116 ,  H01L23/5256 ,  H01L27/11206 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/66833

Abstract: To provide a semiconductor device having mix-loaded therein a nonvolatile memory cell and a field effect transistor at a reduced cost. A method of manufacturing a semiconductor device includes pattering a conductor film by using an additional mask that covers a gate electrode formation region of a memory formation region and exposes a main circuit formation region (field effect transistor formation region) and thereby forming a gate electrode of a nonvolatile memory cell in the memory formation region and then forming an n− type semiconductor region of the nonvolatile memory cell in a semiconductor substrate by ion implantation using the above-mentioned additional mask without changing it to another one.

Abstract translation: 以降低成本提供其中混合加载非易失性存储单元和场效应晶体管的半导体器件。 一种制造半导体器件的方法包括通过使用覆盖存储器形成区域的栅电极形成区域的附加掩模来对导体膜进行图案，并且暴露主电路形成区域（场效应晶体管形成区域），从而形成栅电极 在存储器形成区域中的非易失性存储单元，然后通过使用上述附加掩模的离子注入在半导体衬底中形成非易失性存储单元的n型半导体区域，而不将其改变为另一个。

公开(公告)号：US09685453B2

公开(公告)日：2017-06-20

申请号：US15201609

申请日：2016-07-04

Applicant: Renesas Electronics Corporation

Inventor： Fukuo Owada

IPC: H01L21/8238 ,  H01L27/11575 ,  H01L29/66 ,  H01L21/265 ,  H01L21/266 ,  H01L21/311 ,  H01L27/1157 ,  H01L27/11573 ,  H01L23/525 ,  H01L27/112 ,  H01L27/11568

CPC classification number: H01L27/11575 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/31111 ,  H01L21/31116 ,  H01L23/5256 ,  H01L27/11206 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/66833

Abstract: To provide a semiconductor device having mix-loaded therein a nonvolatile memory cell and a field effect transistor at a reduced cost. A method of manufacturing a semiconductor device includes pattering a conductor film by using an additional mask that covers a gate electrode formation region of a memory formation region and exposes a main circuit formation region (field effect transistor formation region) and thereby forming a gate electrode of a nonvolatile memory cell in the memory formation region and then forming an n− type semiconductor region of the nonvolatile memory cell in a semiconductor substrate by ion implantation using the above-mentioned additional mask without changing it to another one.

公开(公告)号：US20160315093A1

公开(公告)日：2016-10-27

申请号：US15201609

申请日：2016-07-04

Applicant: Renesas Electronics Corporation

Inventor： Fukuo Owada

IPC: H01L27/115 ,  H01L23/525 ,  H01L27/112

CPC classification number: H01L27/11575 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/31111 ,  H01L21/31116 ,  H01L23/5256 ,  H01L27/11206 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/66833

Abstract: To provide a semiconductor device having mix-loaded therein a nonvolatile memory cell and a field effect transistor at a reduced cost. A method of manufacturing a semiconductor device includes pattering a conductor film by using an additional mask that covers a gate electrode formation region of a memory formation region and exposes a main circuit formation region (field effect transistor formation region) and thereby forming a gate electrode of a nonvolatile memory cell in the memory formation region and then forming an n−type semiconductor region of the nonvolatile memory cell in a semiconductor substrate by ion implantation using the above-mentioned additional mask without changing it to another one.

Abstract translation: 以降低成本提供其中混合加载非易失性存储单元和场效应晶体管的半导体器件。 一种制造半导体器件的方法包括通过使用覆盖存储器形成区域的栅电极形成区域的附加掩模来对导体膜进行图案，并且暴露主电路形成区域（场效应晶体管形成区域），从而形成栅电极 在存储器形成区域中的非易失性存储单元，然后通过使用上述附加掩模的离子注入在半导体衬底中形成非易失性存储单元的n型半导体区域，而不将其改变为另一个。

公开(公告)号：US09406813B2

公开(公告)日：2016-08-02

申请号：US15040935

申请日：2016-02-10

Applicant: Renesas Electronics Corporation

Inventor： Fukuo Owada

IPC: H01L21/336 ,  H01L29/792 ,  H01L27/115 ,  H01L29/423

CPC classification number: H01L29/792 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02238 ,  H01L21/02326 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/511 ,  H01L29/518 ,  H01L29/66833

Abstract: To provide a semiconductor device with nonvolatile memory, having improved performance.A memory cell has control and memory gate electrodes on a semiconductor substrate via an insulating film and another insulating film having first, second, and third films stacked one after another in order of mention, respectively. The memory and control gate electrodes are adjacent to each other via the stacked insulating film. The second insulating film has a charge accumulation function. The first and third insulating films each have a band gap greater than that of the second insulating film. An inner angle of the second insulating film between a portion extending between the semiconductor substrate and the memory gate electrode and a portion extending between the control gate electrode and the memory gate electrode is ≧90°. An inner angle of the corner portion between the lower surface and the side surface of the memory gate electrode is

公开(公告)号：US20130135921A1

公开(公告)日：2013-05-30

申请号：US13682578

申请日：2012-11-20

Applicant: Renesas Electronics Corporation

Inventor： Fukuo Owada

IPC: G11C11/21

CPC classification number: G11C11/21 ,  G11C14/009

Abstract: A first ReRAM unit having a resistance change layer is provided between a first access transistor configuring the SRAM and a first bit line, and a second ReRAM unit having a resistance change layer is provided between a second access transistor and a second bit line. When a low potential (L=0V) is held at a first storage node and a high potential (H=1.5V) is held at a second storage node at the end of a normal operation period of the SRAM, the first ReRAM unit is set to ON state (ON), and the second ReRAM unit is set to OFF state (OFF); accordingly, the retained data of the SRAM is written in to the ReRAM units. When the SRAM returns to the normal operation again, data corresponding to the storage nodes are written back and the ReRAM units are both set to ON state (reset).

Abstract translation: 具有电阻变化层的第一ReRAM单元设置在构成SRAM的第一存取晶体管和第一位线之间，并且具有电阻变化层的第二ReRAM单元设置在第二存取晶体管和第二位线之间。 当在第一存储节点处保持低电位（L = 0V）并且在SRAM的正常工作周期结束时在第二存储节点处保持高电位（H = 1.5V）时，第一ReRAM单元是 设置为ON状态（ON），第二个ReRAM单元设置为OFF状态（OFF）; 因此，SRAM的保留数据被写入ReRAM单元。 当SRAM再次返回到正常操作时，对应于存储节点的数据被写回，并且ReRAM单元都被设置为ON状态（复位）。