A first ReRAM unit having a resistance change layer is provided between a first access transistor configuring the SRAM and a first bit line, and a second ReRAM unit having a resistance change layer is provided between a second access transistor and a second bit line. When a low potential (L=0V) is held at a first storage node and a high potential (H=1.5V) is held at a second storage node at the end of a normal operation period of the SRAM, the first ReRAM unit is set to ON state (ON), and the second ReRAM unit is set to OFF state (OFF); accordingly, the retained data of the SRAM is written in to the ReRAM units. When the SRAM returns to the normal operation again, data corresponding to the storage nodes are written back and the ReRAM units are both set to ON state (reset).