公开(公告)号：US20160056254A1

公开(公告)日：2016-02-25

申请号：US14931000

申请日：2015-11-03

Applicant: Renesas Electronics Corporation

Inventor： Kazunobu OTA ,  Hirokazu SAYAMA ,  Hidekazu ODA

IPC: H01L29/423 ,  H01L29/51 ,  H01L27/092

CPC classification number: H01L29/42368 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/265 ,  H01L21/28017 ,  H01L21/28158 ,  H01L21/823814 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/092 ,  H01L29/517 ,  H01L29/518

Abstract: A method of manufacturing a semiconductor device with NMOS and PMOS transistors is provided. The semiconductor device can lessen a short channel effect, can reduce gate-drain current leakage, and can reduce parasitic capacitance due to gate overlaps, thereby inhibiting a reduction in the operating speed of circuits. An N-type impurity such as arsenic is ion implanted to a relatively low concentration in the surface of a silicon substrate (1) in a low-voltage NMOS region (LNR) thereby to form extension layers (61). Then, a silicon oxide film (OX2) is formed to cover the whole surface of the silicon substrate (1). The silicon oxide film (OX2) on the side surfaces of gate electrodes (51-54) is used as an offset sidewall. Then, boron is ion implanted to a relatively low concentration in the surface of the silicon substrate (1) in a low-voltage PMOS region (LPR) thereby to form P-type impurity layers (621) later to be extension layers (62).

公开(公告)号：US20230010383A1

公开(公告)日：2023-01-12

申请号：US17835541

申请日：2022-06-08

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takayuki IGARASHI ,  Hirokazu SAYAMA

IPC: H01L23/00

Abstract: A semiconductor device including an element isolation in a trench formed in an upper surface of a semiconductor substrate, a trench isolation including a void in a trench directly under the element isolation, and a Cu wire with Cu ball connected to a pad on the semiconductor substrate, is formed. The semiconductor device has a circular trench isolation arrangement prohibition region that overlaps the end portion of the Cu ball in plan view, and the trench isolation is separated from the trench isolation arrangement prohibition region in plan view.

公开(公告)号：US20210313467A1

公开(公告)日：2021-10-07

申请号：US17353079

申请日：2021-06-21

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hirokazu SAYAMA ,  Kazunobu OHTA ,  Hidekazu ODA ,  Kouhei SUGIHARA

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/3215 ,  H01L21/8238 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/108 ,  H01L27/11 ,  H01L29/49

Abstract: A gate insulating film and a gate electrode of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate. Using the gate electrode as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode is amorphized. Subsequently, a silicon oxide film is provided to cover the gate electrode, at a temperature which is less than the one at which recrystallization of the gate electrode occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode, and high tensile stress is applied to a channel region under the gate electrode. As a result, carrier mobility of the nMOS transistor is enhanced.

公开(公告)号：US20150325486A1

公开(公告)日：2015-11-12

申请号：US14797967

申请日：2015-07-13

Applicant: Renesas Electronics Corporation

Inventor： Hirokazu SAYAMA

IPC: H01L21/8238 ,  H01L29/10 ,  H01L21/265

CPC classification number: H01L29/78 ,  H01L21/26513 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0922 ,  H01L29/0692 ,  H01L29/1079 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/66477 ,  H01L29/66659 ,  H01L29/7835

Abstract: Provided are a semiconductor device having a high breakdown voltage and attaining the restraint of the action of a parasite bipolar transistor, and a method for producing the device. A high-breakdown-voltage p-channel-type transistor included in the semiconductor device has a first n-type semiconductor layer arranged in a semiconductor substrate and at a main-surface-side (upside) of a p-type region in the semiconductor substrate, and a local n-type buried region arranged just below a first p-type dopant region to contact the first n-type semiconductor layer.

Abstract translation: 提供具有高击穿电压并实现寄生双极晶体管的作用的限制的半导体器件及其制造方法。 包括在半导体器件中的高耐压p沟道型晶体管具有布置在半导体衬底中的第一n型半导体层和半导体中的p型区域的主表面侧（上侧） 衬底和布置在第一p型掺杂剂区域正下方的接触第一n型半导体层的局部n型掩埋区域。

公开(公告)号：US20140024194A1

公开(公告)日：2014-01-23

申请号：US14038981

申请日：2013-09-27

Applicant: Renesas Electronics Corporation

Inventor： Hirokazu SAYAMA ,  Kazunobu Ohta ,  Hidekazu Oda ,  Kouhei Sugihara

IPC: H01L29/66

CPC classification number: H01L29/7845 ,  H01L21/26506 ,  H01L21/32155 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823443 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823835 ,  H01L21/823842 ,  H01L27/10805 ,  H01L27/10844 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/7842 ,  H01L29/7848

Abstract: A gate insulating film and a gate electrode of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate. Using the gate electrode as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode is amorphized. Subsequently, a silicon oxide film is provided to cover the gate electrode, at a temperature which is less than the one at which recrystallization of the gate electrode occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode, and high tensile stress is applied to a channel region under the gate electrode. As a result, carrier mobility of the nMOS transistor is enhanced.

公开(公告)号：US20150340287A1

公开(公告)日：2015-11-26

申请号：US14817048

申请日：2015-08-03

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hirokazu SAYAMA

IPC: H01L21/8234

CPC classification number: H01L21/823412 ,  H01L21/823418 ,  H01L21/823814 ,  H01L21/823857 ,  H01L21/823892 ,  H01L27/0922

Abstract: A semiconductor device in which a reliable high voltage p-channel transistor is formed without an increase in cost and the number of manufacturing steps. The transistor includes: a semiconductor substrate having a main surface and a p-type region therein; a p-type well region located over the p-type region and in the main surface, having a first p-type impurity region to obtain a drain electrode; an n-type well region adjoining the p-type well region along the main surface and having a second p-type impurity region to obtain a source electrode; a gate electrode between the first and second p-type impurity regions along the main surface; and a p-type buried channel overlying the n-type well region and extending along the main surface. The border between the n-type and p-type well regions is nearer to the first p-type impurity region than the gate electrode end near to the first p-type impurity region.

Abstract translation: 一种半导体器件，其中形成可靠的高压p沟道晶体管，而不增加成本和制造步骤的数量。 晶体管包括：其中具有主表面和p型区域的半导体衬底; 位于p型区域和主表面上的p型阱区，具有第一p型杂质区域以获得漏电极; 沿着主表面邻接p型阱区并具有第二p型杂质区以获得源电极的n型阱区; 沿着主表面的第一和第二p型杂质区之间的栅电极; 以及覆盖n型阱区并沿主表面延伸的p型掩埋沟道。 n型和p型阱区之间的边界比靠近第一p型杂质区的栅电极端更靠近第一p型杂质区。

公开(公告)号：US20150194428A1

公开(公告)日：2015-07-09

申请号：US14662276

申请日：2015-03-19

Applicant: Renesas Electronics Corporation

Inventor： Kazunobu OTA ,  Hirokazu SAYAMA ,  Hidekazu ODA

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L29/42368 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/265 ,  H01L21/28017 ,  H01L21/28158 ,  H01L21/823814 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/092 ,  H01L29/517 ,  H01L29/518

Abstract: A method of manufacturing a semiconductor device with NMOS and PMOS transistors is provided. The semiconductor device can lessen a short channel effect, can reduce gate-drain current leakage, and can reduce parasitic capacitance due to gate overlaps, thereby inhibiting a reduction in the operating speed of circuits. An N-type impurity such as arsenic is ion implanted to a relatively low concentration in the surface of a silicon substrate (1) in a low-voltage NMOS region (LNR) thereby to form extension layers (61). Then, a silicon oxide film (OX2) is formed to cover the whole surface of the silicon substrate (1). The silicon oxide film (OX2) on the side surfaces of gate electrodes (51-54) is used as an offset sidewall. Then, boron is ion implanted to a relatively low concentration in the surface of the silicon substrate (1) in a low-voltage PMOS region (LPR) thereby to form P-type impurity layers (621) later to be extension layers (62).

公开(公告)号：US20130130457A1

公开(公告)日：2013-05-23

申请号：US13743012

申请日：2013-01-16

Applicant: Renesas Electronics Corporation

Inventor： Hirokazu SAYAMA ,  Kazunobu Ohta ,  Hidekazu Oda ,  Kouhei Sugihara

IPC: H01L21/8234

CPC classification number: H01L29/7845 ,  H01L21/26506 ,  H01L21/32155 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823443 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823835 ,  H01L21/823842 ,  H01L27/10805 ,  H01L27/10844 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/7842 ,  H01L29/7848

Abstract: A gate insulating film and a gate electrode of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate. Using the gate electrode as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode is amorphized. Subsequently, a silicon oxide film is provided to cover the gate electrode, at a temperature which is less than the one at which recrystallization of the gate electrode occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode, and high tensile stress is applied to a channel region under the gate electrode. As a result, carrier mobility of the nMOS transistor is enhanced.

Abstract translation: 用于形成nMOS晶体管的非绝缘硅栅极绝缘膜和栅电极设置在硅衬底上。 使用栅电极作为掩模，注入具有较大质量数（70以上）的诸如As离子或Sb离子的n型掺杂剂，以形成nMOS晶体管的源极/漏极区域，由此栅极电极 非晶化 随后，提供氧化硅膜以覆盖栅电极，其温度小于栅电极发生再结晶的温度。 此后，在约1000℃的温度下进行热处理，由此在栅极上施加高的压缩残余应力，并且对栅电极下方的沟道区域施加高的拉伸应力。 结果，增强了nMOS晶体管的载流子迁移率。

公开(公告)号：US20210249353A1

公开(公告)日：2021-08-12

申请号：US16784960

申请日：2020-02-07

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hirokazu SAYAMA ,  Fumihiko HAYASHI ,  Junjiro SAKAI

IPC: H01L23/535 ,  H01L21/74 ,  H01L21/762 ,  H01L21/764

Abstract: A semiconductor device includes a semiconductor substrate, a semiconductor layer, a first insulating film, and a conductive film. The semiconductor layer is formed on the semiconductor substrate. A first trench reaching the semiconductor substrate is formed within the semiconductor layer. The first insulating film is formed on the inner side surface of the first trench such that a portion of the semiconductor substrate is exposed in the first trench. The conductive film is electrically connected with the semiconductor substrate and formed on the inner side surface of the first trench through the first insulating film. In plan view, a first length of the first trench in an extending direction of the first trench is greater than a second length of the first trench in a width direction perpendicular to the extending direction, and equal to or less than 30 μm.

公开(公告)号：US20180069119A1

公开(公告)日：2018-03-08

申请号：US15806535

申请日：2017-11-08

Applicant: Renesas Electronics Corporation

Inventor： Hirokazu SAYAMA ,  Kazunobu OHTA ,  Hidekazu ODA ,  Kouhei SUGIHARA

IPC: H01L29/78 ,  H01L21/265 ,  H01L29/66 ,  H01L29/49 ,  H01L27/11 ,  H01L27/108 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/3215

CPC classification number: H01L29/7845 ,  H01L21/26506 ,  H01L21/32155 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823443 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823835 ,  H01L21/823842 ,  H01L27/10805 ,  H01L27/10844 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/7842 ,  H01L29/7848

Abstract: A gate insulating film and a gate electrode of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate. Using the gate electrode as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode is amorphized. Subsequently, a silicon oxide film is provided to cover the gate electrode, at a temperature which is less than the one at which recrystallization of the gate electrode occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode, and high tensile stress is applied to a channel region under the gate electrode. As a result, carrier mobility of the nMOS transistor is enhanced.