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公开(公告)号：US11418206B2
公开(公告)日：2022-08-16
申请号：US17333063
申请日：2021-05-28
Applicant: REALTEK SEMICONDUCTOR CORPORATION
Inventor： Shih-Hsiung Huang , Ying-Cheng Wu , Chien-Ming Wu , Kai-Yin Liu
Abstract: A flash analog to digital converter includes double differential comparator circuits and a calibration circuit. Each double differential comparator circuit compares a first input signal with a corresponding voltage in a first set of reference voltages, and compares a second input signal with a corresponding voltage in a second set of reference voltages, in order to generate a corresponding signal in first signals. The calibration circuit outputs a first test signal to be the first input signal and outputs a second test signal to be the second input signal in a test mode, and calibrates a common mode level of each of the first input signal and the second input signal, or calibrates at least one first reference voltage in the first set of reference voltages and at least one second reference voltage in the second set of reference voltages according to a distribution of the first signals.
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公开(公告)号：US11133961B2
公开(公告)日：2021-09-28
申请号：US17147495
申请日：2021-01-13
Applicant: REALTEK SEMICONDUCTOR CORPORATION
Inventor： Chien-Ming Wu , Chung-Ming Tseng
Abstract: The present disclosure discloses a communication apparatus including a receiver circuit and a transmitter circuit having a signal processing circuit and a DAC circuit having a primary conversion circuit and a first hybrid conversion circuit. The primary conversion circuit converts and transmits a transmission signal from the signal processing circuit to a signal transmission path. The first hybrid conversion circuit converts the transmission signal to a first receiver resistor to generate a voltage drop. The receiver circuit receives a first actual receiving signal through the signal transmission path and the first receiver resistor. The primary conversion circuit operates according to a first current including a first and a second part currents and the first hybrid conversion circuit operates according to a second current. The first part current does not change according to a resistive change. The second part current and the second current change according to the resistive change.
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公开(公告)号：US10608429B2
公开(公告)日：2020-03-31
申请号：US15476169
申请日：2017-03-31
Applicant: REALTEK SEMICONDUCTOR CORPORATION
Inventor： Tay-Her Tsaur , Cheng-Cheng Yen , Chien-Ming Wu , Cheng-Pang Chan
Abstract: This disclosure provides an ESD protection circuit coupled to a first and a second terminals of a differential-pair circuit. The ESD protection circuit includes: an ESD sensing unit coupled to the first and the second terminals and sensing electrical changes at the first and the second terminals to generate a first trigger signal; and a first discharging unit coupled to the ESD sensing unit and turning on a first discharging path according to the first trigger signal.
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公开(公告)号：US10026544B2
公开(公告)日：2018-07-17
申请号：US15244900
申请日：2016-08-23
Applicant: Realtek Semiconductor Corporation
Inventor： Chien-Ming Wu
Abstract: The present invention discloses a common mode noise restrainer applicable to Ethernet, comprising: a circuit side configured to connect with an integrated circuit; a cable side configured to connect with a cable; a plurality of transformers set between the circuit side and the cable side; and a plurality of common mode chokes composed of a first part of the common mode chokes and a second part of the common mode chokes in which the first part of the common mode chokes is set between the circuit side and the plurality of transformers and the second part of the common mode chokes is set between the cable side and the plurality of transformers while the one or more transformer(s) connected with the first part of the common mode chokes are not identical to the one or more transformer(s) connected with the second part of the common mode chokes.
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公开(公告)号：US11496145B2
公开(公告)日：2022-11-08
申请号：US17400152
申请日：2021-08-12
Applicant: REALTEK SEMICONDUCTOR CORPORATION
Inventor： Shih-Hsiung Huang , Pan Zhang , Kai-Yin Liu , Chien-Ming Wu
Abstract: A pipeline analog to digital converter (ADC) includes converter circuitries, a detector circuitry, and a clock generator circuit. The converter circuitries sequentially convert an input signal to be digital codes. One of the converter circuitries includes a sub-ADC circuit and a multiplying digital to analog converter (MDAC) circuit. The sub-ADC circuit performs a quantization according to a first signal to generate a corresponding one of the digital codes, in which the first signal is the input signal or a previous stage residue signal. The MDAC circuit processes the corresponding one of the digital codes in response to a first clock signal, in order to generate a current stage residue signal. The detector circuitry detects whether the quantization is complete, in order to generate a control signal. The clock generator circuit adjusts a timing of the first clock signal according to the control signal.
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Patent Agency Ranking
公开(公告)号：US11245435B2
公开(公告)日：2022-02-08
申请号：US16993312
申请日：2020-08-14
Applicant: REALTEK SEMICONDUCTOR CORPORATION
Inventor： Chien-Ming Wu , Chia-Lin Chang
Abstract: An echo cancellation circuit is coupled to a receiving circuit and a transmitting circuit of an electronic device, and the transmitting circuit includes an output transistor. The echo cancellation circuit includes first and second transistors, first and second resistor-capacitor networks (RC networks), and first and second resistors. The first transistor has a first gate, a first drain and a first source. The second transistor has a second gate, a second drain and a second source. The first drain and the second drain are coupled to the receiving circuit. The first RC network is coupled between the gate of the output transistor and the first gate. The second RC network is coupled between the first gate and the second gate. The first resistor is coupled between the first source and a reference voltage. The second resistor is coupled between the second source and the reference voltage.
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公开(公告)号：US11128272B2
公开(公告)日：2021-09-21
申请号：US16428109
申请日：2019-05-31
Applicant: REALTEK SEMICONDUCTOR CORPORATION
Inventor： Chien-Ming Wu
Abstract: Disclosed are a dual-path analog-front-end (AFE) circuit and a dual-path signal receiver characterized by high linearity. The dual-path AFE circuit includes a first reception circuit, a second reception circuit and a multiplexer. The first reception circuit is configured to generate a first analog input signal according to a reception signal in a first mode and configured to be coupled to a first constant-voltage terminal via a first switch circuit in a second mode. The second reception circuit is configured to generate a second analog input signal according to the reception signal in the second mode and configured to be coupled to a second constant-voltage terminal via a second switch circuit in the first mode. The multiplexer is configured to output the first analog input signal in the first mode and output the second analog input signal in the second mode.
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公开(公告)号：US10931101B2
公开(公告)日：2021-02-23
申请号：US15878817
申请日：2018-01-24
Applicant: REALTEK SEMICONDUCTOR CORPORATION
Inventor： Chien-Ming Wu , Jian-Ru Lin , Liang-Huan Lei , Cheng-Pang Chan
Abstract: The present invention discloses an electrostatic discharge (ESD) protection circuit, including: a first terminal configured to receive a first voltage; a second terminal configured to receive a second voltage; a detection voltage generating circuit configured to provide a detection voltage according to the first voltage and the second voltage; a warning circuit configured to generate a control signal according to the detection voltage, in which the control signal indicates a normal condition when the detection voltage satisfies predetermined voltage setting, and the control signal indicates an abnormal condition when the detection voltage does not satisfy the predetermined voltage setting; and a protected circuit configured to carry out a self-protection operation when receiving the control signal indicating the abnormal condition.
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公开(公告)号：US10700516B2
公开(公告)日：2020-06-30
申请号：US15894269
申请日：2018-02-12
Applicant: REALTEK SEMICONDUCTOR CORPORATION
Inventor： Chien-Ming Wu
Abstract: The present invention discloses an electrostatic discharge (ESD) protection circuit including: a first terminal configured to provide a first voltage having a first value in a normal mode; a second terminal configured to provide a second voltage having a second value in the normal mode; a detection circuit configured to provide a detection voltage according to the first and second voltages; and a protection circuit configured to operate in one of the normal mode and an ESD mode according to the detection voltage. When the difference between a value of the detection voltage and an average of the first and second values reaches a predetermined threshold, the protection circuit enters the ESD mode from the normal mode, and thereby has a first path between the first terminal and a grounding terminal and/or a second path between the second terminal and the grounding terminal be conductive for discharging abnormal energy.
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公开(公告)号：US10396725B2
公开(公告)日：2019-08-27
申请号：US15867676
申请日：2018-01-10
Applicant: Realtek Semiconductor Corporation
Inventor： Chien-Ming Wu , Liang-Huan Lei , Shih-Hsiung Huang , Chih-Lung Chen
Abstract: An amplifier includes an output stage circuit and a compensation circuit. The output stage circuit includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The compensation circuit includes a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor. The first capacitor is coupled between the first input terminal and the second output terminal, and is configured to operate as a first Miller capacitor. The second capacitor is coupled between the second input terminal and the first output terminal, and is configured to operate as a second Miller capacitor. The third capacitor and the fourth capacitor are configured to alternately operate as the first Miller capacitor and the second Miller capacitor according to at least one clock signal.
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