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公开(公告)号：US12155388B2
公开(公告)日：2024-11-26
申请号：US18118755
申请日：2023-03-08
Applicant: REALTEK SEMICONDUCTOR CORPORATION
Inventor： Liang-Huan Lei
Abstract: A comparator includes an input pair circuit, an isolation circuit, and a latch circuit. The input pair circuit receives first and second input signals to generate first and second signals. The isolation circuit is selectively turned on according to a clock signal to transmit the first signal from the input pair circuit to a first output node and transmit the second signal from the input pair circuit to a second output node. The latch circuit adjusts a level of the first output node to generate a first output signal, adjusts a level of the second output node to generate a second output signal, and selectively resets the levels of the first and the second output nodes according to the clock signal. When the latch circuit resets the levels of the first and the second output nodes, the isolation circuit is not turned on.
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公开(公告)号：US11546066B2
公开(公告)日：2023-01-03
申请号：US17131840
申请日：2020-12-23
Applicant: REALTEK SEMICONDUCTOR CORPORATION
Inventor： Liang-Huan Lei , Shih-Hsiung Huang
IPC: H04B17/11 , H04B1/02 , H04B17/19 , H03K19/00 , H03K19/0185
Abstract: A transmitter device includes a transmitter circuit, a voltage generator circuit, and a calibration circuit. The transmitter circuit is configured to selectively operate in a calibration mode or a normal mode in response to a first control signal, in which the transmitter circuit has a first output terminal and a second output terminal. The voltage generator circuit is configured to generate a bias voltage, in which the bias voltage has a first level in the calibration mode and has a second level in the normal mode, and the first level is different from the second level. The calibration circuit is configured to be turned on in the calibration mode according to the bias voltage and a second control signal, in order to calibrate a level of the first output terminal and a level of the second output terminal.
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公开(公告)号：US11057042B2
公开(公告)日：2021-07-06
申请号：US16816452
申请日：2020-03-12
Applicant: Realtek Semiconductor Corporation
Inventor： Chih-Chieh Yang , Shih-Hsiung Huang , Liang-Huan Lei
Abstract: A digital-to-analog converter (DAC) device includes a current-steering DAC circuitry and a calibration circuitry. The current-steering DAC circuitry generates a first signal according to multiple least significant bits of an input signal, and generates a second signal according to multiple most significant bits of the input signal. The calibration circuitry performs a non-binary search algorithm to generate a calibration signal in response to a comparison result of the first signal and the second signal, in order to calibrate the current-steering DAC circuitry according to the calibration signal.
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公开(公告)号：US10598726B2
公开(公告)日：2020-03-24
申请号：US16136723
申请日：2018-09-20
Applicant: REALTEK SEMICONDUCTOR CORPORATION
Inventor： Liang-Huan Lei , Shih-Hsiung Huang , Chih-Lung Chen
IPC: G01R31/317 , G01R31/3187 , G01R31/319
Abstract: A self-test circuit and a self-test method for a comparator are provided. A first output terminal of the comparator is coupled to an input terminal of a first inverter, and a second output terminal of the comparator is coupled to an input terminal of a second inverter. The comparator operates in a reset phase or a comparison phase according to a clock. The self-test method includes steps of: coupling the first output terminal and the second output terminal so that the comparator enters a test mode; and in the test mode, controlling the comparator to operate in the reset phase or the comparison phase according to the clock. In the test mode, the first output terminal and the second output terminal have substantially the same voltage.
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公开(公告)号：US12003234B2
公开(公告)日：2024-06-04
申请号：US18098132
申请日：2023-01-18
Applicant: REALTEK SEMICONDUCTOR CORPORATION
Inventor： Liang-Huan Lei
IPC: H03K17/687
CPC classification number: H03K17/6872
Abstract: A bootstrapped switch includes a sampling transistor, a bootstrapped circuit, and a buffer circuit. The sampling transistor is configured to be selectively turned on according to a level of a control node, in order to transmit an input signal from a first terminal of the sampling transistor to a second terminal of the sampling transistor, in which a body of the sampling transistor is configured to receive a buffer signal. The bootstrapped circuit is configured to pull up the level of the control node, such that a constant voltage difference is present between the control node and the first terminal of the sampling transistor during a turn-on interval of the sampling transistor. The buffer circuit is configured to generate the buffer signal according to the input signal.
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Patent Agency Ranking
公开(公告)号：US11567522B2
公开(公告)日：2023-01-31
申请号：US17405380
申请日：2021-08-18
Applicant: REALTEK SEMICONDUCTOR CORPORATION
Inventor： Che-Wei Chang , Kai-Yin Liu , Liang-Huan Lei , Shih-Hsiung Huang
Abstract: Disclosed is a voltage reference buffer circuit including a first, second, third, and fourth bias generators and a first, second, third, and fourth driving components. The first, second, third, and fourth bias generators generate bias voltages to control the first, second, third, and fourth driving components respectively. The first, second, third, and fourth driving components are coupled in sequence, wherein the first and second driving components are different types of transistors and jointly output a first reference voltage, the third and fourth driving components are different types of transistors and jointly output a second reference voltage, and the group of the first and second driving components is separated from the group of the third and fourth driving components by a resistance load.
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7.发明授权公开(公告)号：US10693487B1
公开(公告)日：2020-06-23
申请号：US16574742
申请日：2019-09-18
Applicant: REALTEK SEMICONDUCTOR CORPORATION
Inventor： Liang-Huan Lei , Shih-Hsiung Huang
IPC: H03M1/46
Abstract: A successive approximation register (SAR) analog-to-digital converter (ADC) and a method of operating the SAR ADC are provided. The SAR ADC converts an analog input signal into a digital code and includes a switch-capacitor digital-to-analog converter (DAC), and the switch-capacitor DAC includes multiple capacitors. The method includes the steps of: switching terminal voltage(s) of at least one target capacitor among the capacitors according to a data in a sampling phase; sampling the analog input signal in the sampling phase; switching the terminal voltage(s) of the at least one target capacitor after the sampling phase; comparing the outputs of the switch-capacitor DAC to obtain multiple comparison results that constitute the digital code; and switching the terminal voltages of a part of the capacitors according to the comparison results.
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公开(公告)号：US10587279B1
公开(公告)日：2020-03-10
申请号：US16385182
申请日：2019-04-16
Applicant: Realtek Semiconductor Corporation
Inventor： Chih-Chieh Yang , Shih-Hsiung Huang , Liang-Huan Lei
Abstract: A digital-to-analog converter (DAC) device includes a DAC circuitry and a calibration circuitry. The DAC circuitry generates a first signal according to least significant bits of an input signal, and generates a second signal according to most significant bits of the input signal. The calibration circuitry compares the first signal with the second signal to generate a calibration signal, and calibrates the DAC circuitry according to the calibration signal. The calibration signal has bits. The calibration circuitry further repeatedly compares the first signal and the second signal to generate a plurality of comparison results when determining at least one bit of the bits, and performs a statistic operation according to the comparison results, in order to adjust the at least one bit, and a number of the at least one bit is less than a number of the bits.
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公开(公告)号：US10931101B2
公开(公告)日：2021-02-23
申请号：US15878817
申请日：2018-01-24
Applicant: REALTEK SEMICONDUCTOR CORPORATION
Inventor： Chien-Ming Wu , Jian-Ru Lin , Liang-Huan Lei , Cheng-Pang Chan
Abstract: The present invention discloses an electrostatic discharge (ESD) protection circuit, including: a first terminal configured to receive a first voltage; a second terminal configured to receive a second voltage; a detection voltage generating circuit configured to provide a detection voltage according to the first voltage and the second voltage; a warning circuit configured to generate a control signal according to the detection voltage, in which the control signal indicates a normal condition when the detection voltage satisfies predetermined voltage setting, and the control signal indicates an abnormal condition when the detection voltage does not satisfy the predetermined voltage setting; and a protected circuit configured to carry out a self-protection operation when receiving the control signal indicating the abnormal condition.
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公开(公告)号：US10396725B2
公开(公告)日：2019-08-27
申请号：US15867676
申请日：2018-01-10
Applicant: Realtek Semiconductor Corporation
Inventor： Chien-Ming Wu , Liang-Huan Lei , Shih-Hsiung Huang , Chih-Lung Chen
Abstract: An amplifier includes an output stage circuit and a compensation circuit. The output stage circuit includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The compensation circuit includes a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor. The first capacitor is coupled between the first input terminal and the second output terminal, and is configured to operate as a first Miller capacitor. The second capacitor is coupled between the second input terminal and the first output terminal, and is configured to operate as a second Miller capacitor. The third capacitor and the fourth capacitor are configured to alternately operate as the first Miller capacitor and the second Miller capacitor according to at least one clock signal.
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