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公开(公告)号：US20240213999A1
公开(公告)日：2024-06-27
申请号：US18519104
申请日：2023-11-27
Applicant: REALTEK SEMICONDUCTOR CORPORATION
Inventor： YAN-HUI WU , Yao-Ming Lu , Tai-Cheng Lee , Chih-Lung Chen , Sheng-Yen Shih
CPC classification number: H03M1/462 , H03M1/0604 , H03M1/0626
Abstract: A continuous-time delta-sigma modulator (CT-DSM) includes a loop filter, a pipelined successive-approximation register analog-to-digital converter (SAR ADC), a feedback circuit, an excess loop delay (ELD) compensation circuit, and a logic circuit. The loop filter generates a first intermediate signal according to an input signal, a feedback signal, and a compensation signal. The pipelined SAR ADC generates a first digital code, a second digital code, a first quantization error signal, and a second quantization error signal according to the first intermediate signal. The feedback circuit generates the feedback signal according to the first digital code, the first quantization error signal, and the second quantization error signal. The ELD compensation circuit generates the compensation signal according to at least one output signal of the feedback circuit. The logic circuit generates an output digital code according to the first digital code and the second digital code.
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公开(公告)号：US11965783B2
公开(公告)日：2024-04-23
申请号：US17143541
申请日：2021-01-07
Applicant: Realtek Semiconductor Corporation
Inventor： Chih-Chan Tu , Chih-Lung Chen
IPC: G01K7/00
CPC classification number: G01K7/00
Abstract: A temperature sensing circuit that includes a bandgap voltage generation circuit, a current mirror branch, a variable resistor, a comparator circuit, a control circuit and a temperature determining circuit. The bandgap voltage generation circuit generates a bandgap voltage. The current mirror branch generates a mirrored current mirrored from the bandgap voltage generation circuit. The variable resistor is electrically coupled to the current mirror branch to receive the mirrored current to generate a variable voltage. The comparator circuit compares the bandgap voltage and the variable voltage to generate a comparison result. The control circuit generates a control signal according to the comparison result to adjust the resistance of the variable resistor and outputs a signal value when the signal value forces the variable voltage to be equal to the bandgap voltage. The temperature determining circuit generates a temperature value according to the signal value.
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公开(公告)号：US11424733B2
公开(公告)日：2022-08-23
申请号：US17395551
申请日：2021-08-06
Applicant: Realtek Semiconductor Corporation
Inventor： Chih-Chan Tu , Chih-Lung Chen , Ka-Un Chan
Abstract: A calibration device includes a signal generator and a processor. The signal generator is configured to provide an input signal to a filter circuit, wherein the filter circuit has a real time constant and is configured to receive the input signal to output an output signal. The processor is configured to calculate a real gain according to the output signal and the input signal, compare the real gain with a target gain to obtain a comparison result and determine whether to adjust the real time constant of the filter circuit according to the comparison result. The present disclosure also provides a calibration method.
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公开(公告)号：US10312925B1
公开(公告)日：2019-06-04
申请号：US16105142
申请日：2018-08-20
Applicant: REALTEK SEMICONDUCTOR CORPORATION
Inventor： Chih-Lung Chen , Ying-Cheng Wu , Shih-Hsiung Huang
Abstract: This invention discloses a multiplying digital-to-analog converter (MDAC) applied to a pipelined analog-to-digital converter (pipelined ADC). The MDAC includes an operational amplifier. The MDAC samples a differential input signal in a sampling phase and performs subtraction and multiplication operations in an amplification phase according to a first reference voltage and a second reference voltage. The common-mode voltage of the first reference voltage and the second reference voltage is not substantially equal to the common-mode voltage of the differential input signal; and/or the voltage difference between the first reference voltage and the second reference voltage is not substantially equal to one half of an allowed maximum peak-to-peak value of the differential input signal. One of the first reference voltage and the second reference voltage can be ground.
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公开(公告)号：US11146216B2
公开(公告)日：2021-10-12
申请号：US16787239
申请日：2020-02-11
Applicant: Realtek Semiconductor Corporation
Inventor： Wei-Chen Lin , Hsuan-Yi Su , Chih-Lung Chen
Abstract: A filter includes M filter circuits. The M filter circuits are sequentially cascaded from an input terminal to an output terminal, in order to generate an output signal according to an input signal, in which M is a positive integer greater than or equal to 2. The M filter circuits include at least one first filter circuit and at least one second filter circuit. Each of the at least one first filter circuit is set to be an active filter circuit, and each of the at least one second filter circuit is set to be a passive filter circuit.
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Patent Agency Ranking
公开(公告)号：US11114981B2
公开(公告)日：2021-09-07
申请号：US16733269
申请日：2020-01-03
Applicant: REALTEK SEMICONDUCTOR CORPORATION
Inventor： Tzung-Ling Tsai , Shu-Lin Chang , Chih-Lung Chen
Abstract: Disclosed is a differential amplifier including an input circuit, a detecting and controlling circuit, and an output circuit. The input circuit outputs input current to two output nodes according to the voltage of a differential input signal and the voltage of a bias node. The detecting and controlling circuit outputs compensative current to the two output nodes according to control bias voltage and the voltage of the bias node, in which the voltage of the bias node and the compensative current relate to the voltage of the differential input signal. The output circuit is coupled to the two output nodes and outputs a differential output signal according to the sum of the input current and the compensative current. Due to the detecting and controlling circuit outputting the compensative current, the differential amplifier prevents itself from entering a deadlock state even though the input current is insufficient or zero.
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公开(公告)号：US10763875B2
公开(公告)日：2020-09-01
申请号：US16524352
申请日：2019-07-29
Applicant: Realtek Semiconductor Corporation
Inventor： Shih-Hsiung Huang , Chih-Lung Chen
Abstract: A switched capacitor circuit includes a first capacitor, a second capacitor, and a switching circuit. The first capacitor is configured to receive a first signal. The second capacitor is configured to receive a second signal. The switching circuit is configured to selectively couple the first capacitor and the second capacitor to an input terminal of a quantizer according to at least one clock signal. In a first configuration of the switching circuit, the first capacitor is configured to store the first signal, and the second capacitor is configured to store the second signal. In a second configuration of the switching circuit, the first capacitor and the second capacitor are stacked in series, in order to transmit a combination of the first signal and the second signal to the input terminal of the quantizer.
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公开(公告)号：US20240329678A1
公开(公告)日：2024-10-03
申请号：US18607606
申请日：2024-03-18
Applicant: REALTEK SEMICONDUCTOR CORPORATION
Inventor： YEN-PO LAI , Chih-Lung Chen , Yi Feng
Abstract: The present disclosure discloses a low dropout regulator apparatus having noise-suppression mechanism. An operational amplifier circuit includes a differential input circuit, an amplifying output circuit and a first and a second resistive components. The differential input circuit is coupled between first connection nodes and a ground terminal to receive a reference voltage and a feedback voltage. The amplifying output circuit includes a first and a second transistor pair circuits. The first transistor pair circuit is coupled between a power supply and second connection nodes. The second transistor pair is coupled between the second connection nodes and the ground terminal and has an amplifying output terminal generating an amplified voltage. The first and the second resistive components are coupled between the first and the second connection nodes. A voltage stabilizing output circuit receives the amplified voltage to generate an output voltage and generates the feedback voltage according to a division thereof.
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公开(公告)号：US11736070B2
公开(公告)日：2023-08-22
申请号：US17406248
申请日：2021-08-19
Applicant: Realtek Semiconductor Corporation
Inventor： Chih-Chan Tu , Chih-Lung Chen , Ka-Un Chan
CPC classification number: H03F1/38 , H03F1/34 , H03F3/45 , H03F2200/153 , H03F2200/408 , H03F2203/45526
Abstract: An amplifier circuit includes a multistage amplifier, a first feedback circuit and a second feedback circuit. The multistage amplifier includes a first-staged amplifier, a last-staged amplifier and at least one middle-staged amplifier cascaded between the first-staged amplifier and the last-staged amplifier. The first feedback circuit is configured to couple a positive output end of the last-staged amplifier to a positive input end of the at least one middle-staged amplifier, or is configured to couple a negative output end of the last-staged amplifier to a negative input end of the at least one middle-staged amplifier. The second feedback circuit is configured to couple the positive output end of the last-staged amplifier to a positive input end of the last-staged amplifier, or is configured to couple the negative output end of the last-staged amplifier to a negative input end of the last-staged amplifier.
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公开(公告)号：US20220149820A1
公开(公告)日：2022-05-12
申请号：US17395551
申请日：2021-08-06
Applicant: Realtek Semiconductor Corporation
Inventor： Chih-Chan Tu , Chih-Lung Chen , Ka-Un Chan
IPC: H03H11/04
Abstract: A calibration device includes a signal generator and a processor. The signal generator is configured to provide an input signal to a filter circuit, wherein the filter circuit has a real time constant and is configured to receive the input signal to output an output signal. The processor is configured to calculate a real gain according to the output signal and the input signal, compare the real gain with a target gain to obtain a comparison result and determine whether to adjust the real time constant of the filter circuit according to the comparison result. The present disclosure also provides a calibration method.
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