公开(公告)号：US11245435B2

公开(公告)日：2022-02-08

申请号：US16993312

申请日：2020-08-14

Applicant: REALTEK SEMICONDUCTOR CORPORATION

Inventor： Chien-Ming Wu ,  Chia-Lin Chang

IPC: H04B3/20 ,  H04B3/23

Abstract: An echo cancellation circuit is coupled to a receiving circuit and a transmitting circuit of an electronic device, and the transmitting circuit includes an output transistor. The echo cancellation circuit includes first and second transistors, first and second resistor-capacitor networks (RC networks), and first and second resistors. The first transistor has a first gate, a first drain and a first source. The second transistor has a second gate, a second drain and a second source. The first drain and the second drain are coupled to the receiving circuit. The first RC network is coupled between the gate of the output transistor and the first gate. The second RC network is coupled between the first gate and the second gate. The first resistor is coupled between the first source and a reference voltage. The second resistor is coupled between the second source and the reference voltage.

公开(公告)号：US11716116B2

公开(公告)日：2023-08-01

申请号：US17711491

申请日：2022-04-01

Applicant: REALTEK SEMICONDUCTOR CORPORATION

Inventor： Hsuan-Ting Ho ,  Liang-Wei Huang ,  Po-Han Lin ,  Chia-Lin Chang

IPC: H04B3/20 ,  H04B3/23 ,  H04L25/02

CPC classification number: H04B3/23 ,  H04L25/0228

Abstract: A method includes: generating a first signal according to a digital signal; filtering the first signal according to first filter coefficients of first filter to generate a second signal; adding a first reference signal with the second signal to generate a third signal; performing digital-to-analog conversion according to the first and third signals to generate and output an echo signal; performing analog-to-digital conversion according to the echo signal to generate a fourth signal; generating a fifth signal according to the digital signal and the fourth signal; and updating the first filter coefficients according to the fifth signal. Generating the fifth signal includes: generating second filter coefficients of second filter; updating the second filter coefficients according to a second reference signal and the fourth signal; obtaining a first and second representative coefficients of the second filter coefficients; and generating the fifth signal according to the first and second representative coefficients.

公开(公告)号：US11171740B2

公开(公告)日：2021-11-09

申请号：US16874307

申请日：2020-05-14

Applicant: REALTEK SEMICONDUCTOR CORPORATION

Inventor： Liang-Wei Huang ,  Yu-Xuan Huang ,  Huan-Chung Chen ,  Chia-Lin Chang

IPC: H04B3/23 ,  H04L1/00

Abstract: The present invention provides a transceiver. The transistor is coupled to a transmission line. The transceiver includes a variable resistor set, a transmitter module, a receiver module, and a digital signal processor. The transmitter module has an output terminal coupled to the variable resistor set and the transmission line. The transmitter module includes a first digital-to-analog converter configured to output an emission current. The receiver module has an input terminal coupled to the transmitter module and the transmission line. When the emission current is fed into the transmission line, a far-end echo is fed into the receiver module. An amplitude of the far-end echo is associated with a resistance value of the transmission line. The digital signal processor adjusts a current value of the emission current from a first default current value to a second default current value based on the amplitude of the far-end echo.

公开(公告)号：US11632229B2

公开(公告)日：2023-04-18

申请号：US17469925

申请日：2021-09-09

Applicant: REALTEK SEMICONDUCTOR CORPORATION

Inventor： Hsuan-Ting Ho ,  Liang-Wei Huang ,  Yang-Bang Li ,  Chia-Lin Chang

IPC: H04B3/00 ,  H04L25/00 ,  H04L7/00

Abstract: A signal transceiver circuit, a method of operating a signal transmitting circuit, and a method of setting a delay circuit are provided. The signal transceiver circuit is used to send an output signal and receive an input signal, and includes: a delay circuit for delaying a first clock to generate a second clock; a first digital-to-analog converter (DAC) for converting a first digital signal into the output signal according to the first clock; a second DAC for converting the first digital signal into an echo cancellation signal according to the second clock; an analog front-end circuit for receiving the input signal and the echo cancellation signal and generating an analog signal; and an analog-to-digital converter (ADC) for converting the analog signal into a second digital signal.

公开(公告)号：US11616530B2

公开(公告)日：2023-03-28

申请号：US17370049

申请日：2021-07-08

Applicant: Realtek Semiconductor Corporation

Inventor： Hsuan-Ting Ho ,  Liang-Wei Huang ,  Kuei-Ying Lu ,  Chia-Lin Chang

IPC: H04B3/23 ,  H04B1/04

Abstract: An echo canceller system includes a data transmitter circuit and an echo canceller circuit. The data transmitter circuit is configured to receive a transmitted signal. The echo canceller circuit includes a first filter. The first filter is configured to generate a first filtered signal according to the transmitted signal and a filter coefficient vector. The filter coefficient vector is updated according to a high-frequency leakage process. The echo canceller circuit is further configured to generate an echo cancelling signal according to the first filtered signal. The data transmitter circuit is further configured to generate an output signal according to a received signal and the echo cancelling signal.

公开(公告)号：US11894856B2

公开(公告)日：2024-02-06

申请号：US17728178

申请日：2022-04-25

Applicant: REALTEK SEMICONDUCTOR CORPORATION

Inventor： Hsuan-Ting Ho ,  Liang-Wei Huang ,  Yun-Chih Tsai ,  Chia-Lin Chang

IPC: H03M1/10

CPC classification number: H03M1/1023 ,  H03M1/1047 ,  H03M1/1042

Abstract: The present invention discloses a DAC method having signal calibration mechanism is provided. Operation states of current sources are controlled to generate an output analog signal by a DAC circuit according to a codeword of an input digital signal. An echo signal is generated by an echo transmission circuit according to the output analog signal. The codeword is mapped to generate an offset signal by a calibration circuit according to a codeword offset mapping table. The offset signal is processed to generate an echo-canceling signal by an echo-canceling circuit. By a calibration parameter calculation circuit, offset amounts are generated according to a difference between the echo signal and the echo-canceling signal, the offset amounts are grouped to perform statistic operation according to the operation states and current offset values are calculated according to calculation among groups and converted to codeword offset values to update the codeword offset mapping table.