Integrated circuit and electrostatic discharge protection method

    公开(公告)号:US11508716B2

    公开(公告)日:2022-11-22

    申请号:US16837044

    申请日:2020-04-01

    Abstract: An integrated circuit includes a load circuit and an electrostatic discharge (ESD) circuit. The load circuit includes a first and a second I/O terminal. The ESD circuit is coupled to the first and the second I/O terminal. The ESD circuit includes a first protection circuit configured to conduct a first ESD current from the first to the second I/O terminal. The first protection circuit includes a first, a second, a third doped region, and a well. The first doped region is coupled to the first I/O terminal, and has a first conductive type. The well is coupled to the first doped region, and has a second conductive type different from the first conductive type. The second doped region is coupled to the well, and has the first conductive type. The third doped region couples the second doped region to the second I/O terminal, and has the second conductive type.

    Regulator
    2.
    发明授权

    公开(公告)号:US09760105B1

    公开(公告)日:2017-09-12

    申请号:US15169715

    申请日:2016-05-31

    CPC classification number: G05F1/575 G05F1/468 G05F1/595 H02H7/10

    Abstract: A regulator includes a driving circuit, an amplifying circuit and an overvoltage protection circuit. The driving circuit is configured to receive an input voltage and provide an output voltage through an output terminal. The amplifying circuit is configured to control the driving circuit according to the output voltage. The overvoltage protection circuit is configured to conduct a first current from the output terminal of the overprotection circuit to a ground terminal. When the overvoltage protection circuit detects that a voltage level of a node coupled to the driving circuit is increased, the overvoltage protection circuit conducts a second current from the output terminal of the overprotection circuit to the ground terminal to lower the output voltage, in which the second current is larger than the first current.

    Current-mirror-based electrostatic discharge clamping circuit and current-mirror-based electrostatic discharge detector

    公开(公告)号:US09948092B2

    公开(公告)日:2018-04-17

    申请号:US14964500

    申请日:2015-12-09

    CPC classification number: H02H9/046

    Abstract: The present invention discloses a current-mirror-based electrostatic discharge (ESD) clamping circuit comprising: a first power terminal; a second power terminal; a current-mirror-based ESD detector; a driver; and an ESD clamping element. The current-mirror-based ESD detector includes: a resistor coupled between the first power terminal and a detection-output-terminal; a semiconductor capacitor coupled between the detection-output-terminal and an ESD triggered current mirror; and the ESD triggered current mirror operable to electrically connect the semiconductor capacitor and/or the detection-output-terminal with the second power terminal according to the level of a driving signal under an ESD operation. The driver is operable to generate the driving signal according to the voltages of the detection-output-terminal and the first and second power terminals. The ESD clamping element is operable to provide a conducting path from the first power terminal to the second power terminal according to the level of the driving signal under the ESD operation.

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