Package architecture utilizing wafer to wafer bonding

    公开(公告)号:US11637050B2

    公开(公告)日:2023-04-25

    申请号:US17219189

    申请日:2021-03-31

    申请人: Qorvo US, Inc.

    摘要: The present disclosure relates to a package architecture and a method for making the same. The disclosed package architecture includes a package carrier, a first device die and a second device die mounted on the package carrier, and a heat spreader. The first device die includes a first device body with a thickness between 5 μm and 130 μm, a die carrier, and an attachment section between the first device body and the die carrier, while the second device die includes a second device body. The first device body and the second device body are formed of different materials. A top surface of the die carrier of the first device die and a top surface of the second device body of the second device die are substantially coplanar. The heat spreader resides over the top surface of the die carrier and the top surface of the second device body.

    PACKAGE ARCHITECTURE UTILIZING WAFER TO WAFER BONDING

    公开(公告)号:US20220319945A1

    公开(公告)日:2022-10-06

    申请号:US17219189

    申请日:2021-03-31

    申请人: Qorvo US, Inc.

    摘要: The present disclosure relates to a package architecture and a method for making the same. The disclosed package architecture includes a package carrier, a first device die and a second device die mounted on the package carrier, and a heat spreader. The first device die includes a first device body with a thickness between 5 μm and 130 μm, a die carrier, and an attachment section between the first device body and the die carrier, while the second device die includes a second device body. The first device body and the second device body are formed of different materials. A top surface of the die carrier of the first device die and a top surface of the second device body of the second device die are substantially coplanar. The heat spreader resides over the top surface of the die carrier and the top surface of the second device body.

    Air cavity package
    6.
    发明授权

    公开(公告)号:US10177064B2

    公开(公告)日:2019-01-08

    申请号:US15364752

    申请日:2016-11-30

    申请人: Qorvo US, Inc.

    摘要: The present disclosure relates to an air-cavity package, which includes a substrate, a base, and a semiconductor die. The substrate includes a substrate body, thermal vias extending through the substrate body, and a metal trace on a bottom side of the substrate body and separate from the thermal vias. The base includes a base body, a perimeter wall extending about a perimeter of the base body, and a signal via structure. Herein, the bottom side of the substrate body resides on the perimeter wall to form a cavity, and the signal via structure extends through the perimeter wall and is electrically coupled to the metal trace. The semiconductor die is mounted on the bottom side of the substrate body, exposed to the cavity, and electrically coupled to the metal trace. The thermal vias conduct heat generated from the semiconductor die toward a top side of the substrate body.

    INTEGRATED CIRCUIT DIE STACKED WITH BACKER DIE INCLUDING CAPACITORS AND THERMAL VIAS

    公开(公告)号:US20220310471A1

    公开(公告)日:2022-09-29

    申请号:US17213974

    申请日:2021-03-26

    申请人: Qorvo US, Inc.

    摘要: The disclosure is directed to an integrated circuit (IC) die stacked with a backer die, including capacitors and thermal vias. The backer die includes a substrate material to contain and electrically insulate one or more capacitors at a back of the IC die. The backer die further includes a thermal material that is more thermally conductive than the substrate material for thermal spreading and increased heat dissipation. In particular, the backer die electrically couples capacitors to the IC die in a stacked configuration while also spreading and dissipating heat from the IC die. Such a configuration reduces an overall footprint of the electronic device, resulting in decreased integrated circuits (IC) packages and module sizes. In other words, instead of placing the capacitors next to the IC die, the capacitors are stacked on top of the IC die, thereby reducing an overall surface area of the package.