公开(公告)号：US11948893B2

公开(公告)日：2024-04-02

申请号：US17557551

申请日：2021-12-21

Applicant: Qorvo US, Inc.

Inventor： Zhunming Du ,  Christopher Sanabria ,  Timothy M. Gittemeier ,  Terry Hon ,  Anthony Chiu ,  Tariq Lodhi

IPC: H01L23/552 ,  H01L23/047 ,  H01L23/66

CPC classification number: H01L23/552 ,  H01L23/047 ,  H01L23/66 ,  H01L2223/6683

Abstract: The disclosure is directed to an electronic device with a lid to manage radiation feedback. The electronic device includes a lid having at least one sidewall and a top wall, as well as a semiconductor positioned within a cavity of the lid. In certain embodiments, the lid includes at least one dielectric material and at least one internal conductive layer at least partially embedded within the at least one dielectric material. In certain embodiments, the lid includes dielectric material, as well as an internal wall extending from the top wall and positioned between an input port and an output port of the semiconductor. Such configurations may suppress any undesirable feedback through the lid between the input port and the output port of the semiconductor.

公开(公告)号：US20230197629A1

公开(公告)日：2023-06-22

申请号：US17557551

申请日：2021-12-21

Applicant: Qorvo US, Inc.

Inventor： Zhunming Du ,  Christopher Sanabria ,  Timothy M. Gittemeier ,  Terry Hon ,  Anthony Chiu ,  Tariq Lodhi

IPC: H01L23/552 ,  H01L23/047 ,  H01L23/66

CPC classification number: H01L23/552 ,  H01L23/047 ,  H01L23/66 ,  H01L2223/6683

Abstract: The disclosure is directed to an electronic device with a lid to manage radiation feedback. The electronic device includes a lid having at least one sidewall and a top wall, as well as a semiconductor positioned within a cavity of the lid. In certain embodiments, the lid includes at least one dielectric material and at least one internal conductive layer at least partially embedded within the at least one dielectric material. In certain embodiments, the lid includes dielectric material, as well as an internal wall extending from the top wall and positioned between an input port and an output port of the semiconductor. Such configurations may suppress any undesirable feedback through the lid between the input port and the output port of the semiconductor.

公开(公告)号：US12136615B2

公开(公告)日：2024-11-05

申请号：US17538517

申请日：2021-11-30

Applicant: Qorvo US, Inc.

Inventor： Matthew Essar ,  Curtis Miller ,  Christopher Sanabria ,  Zhunming Du

IPC: H01L25/16 ,  H01L23/00 ,  H01L23/043 ,  H01L23/492 ,  H01L23/498 ,  H01L23/64 ,  H01L23/66

Abstract: The disclosure is directed to an electronic package with an interposer between integrated circuit dies. At least one inner capacitor (e.g., single layer capacitor) is mounted to the interposer. The electronic package further includes an input passive circuit substrate and an output passive circuit substrate mechanically coupled to the metal base. Use of an interposer to be simultaneously solder attached with integrated circuit dies provides a configuration that improves linearity performance and/or wide video bandwidth of the electronic package (e.g., packages that use epoxy and laminate interposers). Further, such configuration facilitates efficient manufacturing of the electronic package at high volumes.

公开(公告)号：US20240250041A1

公开(公告)日：2024-07-25

申请号：US18592693

申请日：2024-03-01

Applicant: Qorvo US, Inc.

Inventor： Zhunming Du ,  Christopher Sanabria ,  Timothy M. Gittemeier ,  Terry Hon ,  Anthony Chiu ,  Tariq Lodhi

IPC: H01L23/552 ,  H01L23/047 ,  H01L23/66

CPC classification number: H01L23/552 ,  H01L23/047 ,  H01L23/66 ,  H01L2223/6683

Abstract: The disclosure is directed to an electronic device with a lid to manage radiation feedback. The electronic device includes a lid having at least one sidewall and a top wall, as well as a semiconductor positioned within a cavity of the lid. In certain embodiments, the lid includes at least one dielectric material and at least one internal conductive layer at least partially embedded within the at least one dielectric material. In certain embodiments, the lid includes dielectric material, as well as an internal wall extending from the top wall and positioned between an input port and an output port of the semiconductor. Such configurations may suppress any undesirable feedback through the lid between the input port and the output port of the semiconductor.

公开(公告)号：US20230170340A1

公开(公告)日：2023-06-01

申请号：US17538517

申请日：2021-11-30

Applicant: Qorvo US, Inc.

Inventor： Matthew Essar ,  Curtis Miller ,  Christopher Sanabria ,  Zhunming Du

IPC: H01L25/16 ,  H01L23/492 ,  H01L23/00 ,  H01L23/498 ,  H01L23/64 ,  H01L23/66 ,  H01L23/043

CPC classification number: H01L25/165 ,  H01L23/492 ,  H01L24/32 ,  H01L24/29 ,  H01L23/49822 ,  H01L23/642 ,  H01L23/66 ,  H01L24/48 ,  H01L23/043 ,  H01L24/83 ,  H01L2224/32245 ,  H01L2224/29144 ,  H01L2224/29111 ,  H01L2223/6683 ,  H01L2224/48195 ,  H01L2224/83801

Abstract: The disclosure is directed to an electronic package with an interposer between integrated circuit dies. At least one inner capacitor (e.g., single layer capacitor) is mounted to the interposer. The electronic package further includes an input passive circuit substrate and an output passive circuit substrate mechanically coupled to the metal base. Use of an interposer to be simultaneously solder attached with integrated circuit dies provides a configuration that improves linearity performance and/or wide video bandwidth of the electronic package (e.g., packages that use epoxy and laminate interposers). Further, such configuration facilitates efficient manufacturing of the electronic package at high volumes.