公开(公告)号：US20220158343A1

公开(公告)日：2022-05-19

申请号：US17098319

申请日：2020-11-13

Applicant: QUALCOMM Incorporated

Inventor： Muhammad HASSAN ,  Jeremy GOLDBLATT ,  Bhushan Shanti ASURI ,  Jeremy Darren DUNWORTH ,  Abdellatif BELLAOUAR ,  Ravi SRIDHARA ,  Jorge GARCIA

IPC: H01Q3/24 ,  H01Q21/20 ,  H01Q21/12

Abstract: In some aspects, an apparatus includes a transformer including a first inductor, a second inductor, and a third inductor. The apparatus also includes a power amplifier coupled to the first inductor, a first antenna coupled to a first terminal of the second inductor, a second antenna coupled to a second terminal of the second inductor, a first switch coupled between the first terminal of the second inductor and a ground, a second switch coupled between the second terminal of the second inductor and the ground, and a low-noise amplifier coupled to the third inductor.

公开(公告)号：US20180205413A1

公开(公告)日：2018-07-19

申请号：US15872695

申请日：2018-01-16

Applicant: QUALCOMM Incorporated

Inventor： Chirag Dipak PATEL ,  Lai Kan LEUNG ,  Zhang JIN ,  Chinmaya MISHRA ,  Ravi SRIDHARA ,  Youngchang YOON

IPC: H04B1/44 ,  H04W72/04 ,  H04L5/14 ,  H03F1/48 ,  H03F3/19 ,  H03F3/24 ,  H03F1/56

Abstract: Various aspects described herein relate to low-loss multi-band multiplexing schemes for a wireless communications system, for example, a 5th Generation (5G) New Radio (NR) system. In an aspect, a multiplexer for multi-band wireless communications comprises at least one tuning component configured to transmit or receive at least one signal within a frequency band that is selected from a plurality of frequency bands. The multiplexer further comprises at least one combining component, communicatively coupled with the at least one tuning component, configured to transmit or receive the at least one signal within the selected frequency band. In an aspect, the at least one tuning component is integrated on a chip and the at least one combining component is not integrated on the chip.

公开(公告)号：US20180076805A1

公开(公告)日：2018-03-15

申请号：US15265217

申请日：2016-09-14

Applicant: QUALCOMM Incorporated

Inventor： Animesh PAUL ,  Jingcheng ZHUANG ,  Xinhua CHEN ,  Ravi SRIDHARA

IPC: H03K5/156 ,  H03K21/02

CPC classification number: H03K5/1565 ,  H03K21/02

Abstract: Certain aspects of the present disclosure generally relate to methods and apparatus for generating clock signals. For example, certain aspects of the present disclosure provide a clock generation circuit. The clock generation circuit may include a first transistor connected in cascode with a second transistor, wherein an input clock node of the circuit is coupled to gates of the first and second transistors. The clock generation circuit may also include a frequency divider circuit having an input coupled to the input clock node, wherein an output of the frequency divider circuit is coupled to a source of the second transistor, and wherein an output node of the circuit is coupled to drains of the first and second transistors.

公开(公告)号：US20220189886A1

公开(公告)日：2022-06-16

申请号：US17118253

申请日：2020-12-10

Applicant: QUALCOMM Incorporated

Inventor： Muhammad HASSAN ,  Bhushan Shanti ASURI ,  Jeremy Darren DUNWORTH ,  Ravi SRIDHARA

IPC: H01L23/60 ,  H03F3/24 ,  H03F3/195

Abstract: According to certain aspects, a chip includes a pad, a power amplifier, a transformer coupled between an output of the power amplifier and the pad, a transistor coupled between the transformer and a ground, and a first clamp circuit coupled between a gate of the transistor and a drain of the transistor.

公开(公告)号：US20170338940A1

公开(公告)日：2017-11-23

申请号：US15270444

申请日：2016-09-20

Applicant: QUALCOMM Incorporated

Inventor： Marco ZANUSO ,  Mohammad ELBADRY ,  Tsai-Pi HUNG ,  Ravi SRIDHARA ,  Francesco GATTA ,  Jingcheng ZHUANG

IPC: H04L7/033 ,  H04L5/14 ,  H04L29/06 ,  H04W84/04

CPC classification number: H04L7/033 ,  H03L7/14 ,  H03L7/143 ,  H03L7/1976 ,  H03L2207/08 ,  H04L5/14 ,  H04L69/28 ,  H04W84/042

Abstract: A phase discontinuity mitigation implementation within a phased lock loop (PLL) improves throughput of a radio access technology. The throughput is improved by maintaining a phase of the PLL while powering off some devices of the PLL, such as a local oscillator (LO) frequency divider. In one instance, when the PLL is powered down, one or more portions of a delta sigma modulator for the PLL are clocked with a reference clock for the PLL. This implementation maintains phase continuity when the first phase lock loop turns back on.

公开(公告)号：US20230258699A1

公开(公告)日：2023-08-17

申请号：US18306616

申请日：2023-04-25

Applicant: QUALCOMM Incorporated

Inventor： Abdellatif BELLAOUAR ,  Arul BALASUBRAMANIYAN ,  Gurkanwal Singh SAHOTA ,  Muhammad HASSAN ,  Jorge GARCIA ,  Bhushan Shanti ASURI ,  Ravi SRIDHARA ,  Omar Essam EL-AASSAR ,  Chinmaya MISHRA

IPC: G01R21/10 ,  G01R21/133 ,  H03F3/45

CPC classification number: G01R21/10 ,  G01R21/133 ,  H03F3/45475 ,  H03F2200/171 ,  H03F2200/294 ,  H03F2200/451 ,  H03M1/12

Abstract: In certain aspects, a method is provided for measuring power using a resistive element coupled between a power amplifier and an antenna. The method includes squaring a voltage from a first terminal of the resistive element to obtain a first signal, squaring a voltage from a second terminal of the resistive element to obtain a second signal, and generating a measurement signal based on a difference between the first signal and the second signal. In some implementations, the resistive element is implemented with a power switch.

公开(公告)号：US20230253346A1

公开(公告)日：2023-08-10

申请号：US18300256

申请日：2023-04-13

Applicant: QUALCOMM Incorporated

Inventor： Muhammad HASSAN ,  Bhushan Shanti ASURI ,  Jeremy Darren DUNWORTH ,  Ravi SRIDHARA

IPC: H01L23/60 ,  H03F3/195 ,  H03F3/24

CPC classification number: H01L23/60 ,  H03F3/195 ,  H03F3/245 ,  H03F2200/318 ,  H03F2200/441 ,  H03F2200/451 ,  H03F2200/541

Abstract: In certain aspects, a chip includes a pad, and a power amplifier having a first output and a second output. The chip also includes a transformer, wherein the transformer includes a first inductor coupled between a first terminal and a second terminal of the transformer, wherein the first terminal is coupled to the first output of the power amplifier, and the second terminal is coupled to the second output of the power amplifier. The transformer also includes a second inductor coupled between a third terminal and a fourth terminal of the transformer, wherein the third terminal is coupled to the pad. The chip also includes a first switch coupled to the fourth terminal, a shunt inductor coupled in parallel with the first switch, and a low-noise amplifier coupled to the third terminal.

公开(公告)号：US20220018882A1

公开(公告)日：2022-01-20

申请号：US16932589

申请日：2020-07-17

Applicant: QUALCOMM Incorporated

Inventor： Abdellatif BELLAOUAR ,  Arul BALASUBRAMANIYAN ,  Gurkanwal Singh SAHOTA ,  Muhammad HASSAN ,  Jorge GARCIA ,  Bhushan Shanti ASURI ,  Ravi SRIDHARA ,  Omar Essam EL-AASSAR ,  Chinmaya MISHRA

IPC: G01R21/10 ,  H03F3/45 ,  G01R21/133

Abstract: In certain aspects, a method is provided for measuring power using a resistive element coupled between a power amplifier and an antenna. The method includes squaring a voltage from a first terminal of the resistive element to obtain a first signal, squaring a voltage from a second terminal of the resistive element to obtain a second signal, and generating a measurement signal based on a difference between the first signal and the second signal. In some implementations, the resistive element is implemented with a power switch.