公开(公告)号：US20190181843A1

公开(公告)日：2019-06-13

申请号：US15841269

申请日：2017-12-13

Applicant: QUALCOMM Incorporated

Inventor： Animesh PAUL ,  Xinhua CHEN ,  Shailesh RAI

IPC: H03K3/012 ,  H03K3/03 ,  H03K3/356

Abstract: Dividers based on quadrature ring oscillators using conventional latch devices can suffer from high current consumption. This is because there can be a number of short-circuit current paths during the output transitions of the conventional latch devices. To address this issue, a latch device with a novel locking cell is proposed. Unlike the conventional latch device, the transistors of the proposed locking cell may all be of a same transistor type. The configuration of the proposed locking cell eliminates a number of the short-circuit currents compared to the conventional latch device. As a result, power consumption can be reduced.

公开(公告)号：US20180102772A1

公开(公告)日：2018-04-12

申请号：US15290484

申请日：2016-10-11

Applicant: QUALCOMM Incorporated

Inventor： Animesh PAUL ,  Xinhua CHEN

IPC: H03K5/156 ,  H03K5/134

CPC classification number: H03K5/1565 ,  H03K5/134 ,  H03K2005/00026 ,  H04B1/40

Abstract: Certain aspects of the present disclosure generally relate to generating clock signals. For example, certain aspects of the present disclosure provide a multi-stage clock generation circuit. The multi-stage clock generation circuit generally includes a first clock-generation stage comprising first cascode-connected transistors the first cascode-connected transistors having gates coupled to a first input clock node. The multi-stage clock generation circuit may also include a second clock-generation stage comprising second cascode-connected transistors, the second cascode-connected transistors having gates coupled to a second input clock node. A first transistor may be coupled to the second cascode-connected transistors, the first transistor having a gate coupled to drains of the first cascode-connected transistors.

公开(公告)号：US20180076805A1

公开(公告)日：2018-03-15

申请号：US15265217

申请日：2016-09-14

Applicant: QUALCOMM Incorporated

Inventor： Animesh PAUL ,  Jingcheng ZHUANG ,  Xinhua CHEN ,  Ravi SRIDHARA

IPC: H03K5/156 ,  H03K21/02

CPC classification number: H03K5/1565 ,  H03K21/02

Abstract: Certain aspects of the present disclosure generally relate to methods and apparatus for generating clock signals. For example, certain aspects of the present disclosure provide a clock generation circuit. The clock generation circuit may include a first transistor connected in cascode with a second transistor, wherein an input clock node of the circuit is coupled to gates of the first and second transistors. The clock generation circuit may also include a frequency divider circuit having an input coupled to the input clock node, wherein an output of the frequency divider circuit is coupled to a source of the second transistor, and wherein an output node of the circuit is coupled to drains of the first and second transistors.