公开(公告)号：US20190215518A1

公开(公告)日：2019-07-11

申请号：US15866582

申请日：2018-01-10

Applicant: QUALCOMM Incorporated

Inventor： Aravind Alagappan ,  Marc Bosch Ruiz ,  Yu Liu ,  Shyamprasad Chikkerur ,  Yunqing Chen ,  Tushar Singhal ,  Shu Lin ,  Kai Wang ,  Harikrishna Reddy

IPC: H04N19/139 ,  G06T7/269 ,  H04N19/53 ,  G06T7/207

CPC classification number: H04N19/139 ,  G06T7/207 ,  G06T7/269 ,  H04N19/53

Abstract: Methods, systems, and devices for motion analysis are described. Generally, the described techniques provide for computationally efficient and accurate motion analysis. A device may identify frames of a video frame sequence having a defined resolution. The device may downscale the frames to generate a plurality of downsampled images each having a resolution lower than the defined resolution. The device may generate a respective histogram vector for each pixel of each downsampled image and each pixel of the original frames. The device may determine a motion vector candidate based at least in part on the histogram vectors. The device may apply a filter to the motion vector candidates to determine a final motion vector and output an indication of motion between the frames of the video frame sequence based at least in part on the final motion vector for each pixel of the second frame.

公开(公告)号：US20190174135A1

公开(公告)日：2019-06-06

申请号：US16252231

申请日：2019-01-18

Applicant: QUALCOMM Incorporated

Inventor： Shu Lin ,  Mang Li ,  Kai Wang ,  Atul Garg

IPC: H04N19/15 ,  H04N19/433 ,  H04N19/423 ,  H04N19/152 ,  H04N19/66 ,  H04N19/88

Abstract: Video pixel line buffers are widely used for data processing in video codecs. Video data may be packed into buffers configured to store a plurality of words, each word comprising a series of bits. The video data may be associated with two or more channels. In order to reduce realization costs, data blocks from two different channels may be packed from opposite sides of a word in the buffer in opposite directions. In some embodiments, data blocks from two or more physical channels may be mapped to two or more virtual channels, the virtual channels having balanced data block sizes. The data blocks associated with the virtual channels may then be packed to one or more buffers.

公开(公告)号：US09432614B2

公开(公告)日：2016-08-30

申请号：US13801220

申请日：2013-03-13

Applicant: QUALCOMM Incorporated

Inventor： Feng Ge ,  Hariharan G. Lalgudi ,  Sumit Mohan ,  Kai Wang ,  Narendranath Malayath

IPC: H04N19/00 ,  H04N7/01 ,  H04N19/42 ,  H04N19/59 ,  H04N19/33

CPC classification number: H04N7/0117 ,  H04N19/33 ,  H04N19/42 ,  H04N19/59

Abstract: Implementations include video image processing systems, methods, and apparatus for integrated video downscale in a video core. The downscaler computes and writes a display frame to an external memory. This frame may have the same resolution as a target display device (e.g., mobile device). The target display device then reads this display frame, rather than the original higher resolution frame. By enabling downscale during encoding/decoding, the device can conserve resources such as memory bandwidth, memory access, bus bandwidth, and power consumption associated with separately downscaling a frame of video data.

Abstract translation: 实现包括视频图像处理系统，方法和用于在视频核心中集成视频缩减的装置。 缩放器计算并将显示帧写入外部存储器。 该帧可以具有与目标显示设备（例如，移动设备）相同的分辨率。 目标显示设备然后读取该显示帧，而不是原始的较高分辨率帧。 通过在编码/解码期间实现低档，该设备可以节省与分别缩小视频数据帧相关联的资源，例如存储器带宽，存储器访问，总线带宽和功耗。

公开(公告)号：US09154787B2

公开(公告)日：2015-10-06

申请号：US13744128

申请日：2013-01-17

Applicant: Qualcomm Incorporated

Inventor： Sanjeev Kumar ,  Hsiao-Chiang Chuang ,  Shu Xiao ,  Kai Wang ,  Xianglin Wang ,  Wei-Jung Chien ,  Marta Karczewicz ,  Vadim Seregin

IPC: H04N19/50 ,  H04N19/436 ,  H04N19/11 ,  H04N19/156 ,  H04N19/174

CPC classification number: H04N19/50 ,  H04N19/11 ,  H04N19/156 ,  H04N19/174 ,  H04N19/436

Abstract: The techniques of this disclosure are generally related to parallel coding of video units that reside along rows or columns of blocks in largest coding units. For example, the techniques include removing intra-prediction dependencies between two video units in different rows or columns to allow for parallel coding of rows or columns of the video units.

Abstract translation: 本公开的技术通常涉及以最大编码单元沿着行或列的行驻留的视频单元的并行编码。 例如，这些技术包括去除不同行或列中的两个视频单元之间的帧内预测依赖性，以允许视频单元的行或列的并行编码。

公开(公告)号：US20150215621A1

公开(公告)日：2015-07-30

申请号：US14332192

申请日：2014-07-15

Applicant: QUALCOMM Incorporated

Inventor： Meng Liu ,  Hsiao-Chiang Chuang ,  Hariharan Ganesh Lalgudi ,  Srikanth Alaparthi ,  Cheng-Teh Hsieh ,  Harikrishna Madadi Reddy ,  Kai Wang

IPC: H04N19/124 ,  H04N19/184 ,  H04N19/147

CPC classification number: H04N19/124 ,  H04N19/115 ,  H04N19/14 ,  H04N19/149 ,  H04N19/176

Abstract: In one example, a method of encoding video data includes allocating, based on a complexity of a reference frame and a quantity of bits allocated to a current frame, a quantity of bits to a current largest coding unit (LCU) included in the current frame. In this example, the method also includes determining, based on the quantity of bits allocated to the current LCU, a quantization parameter (QP) for the current LCU, and encoding the current LCU with the determined QP.

Abstract translation: 在一个示例中，视频数据的编码方法包括基于参考帧的复杂度和分配给当前帧的比特数来分配当前帧中包括的当前最大编码单元（LCU）的比特量 。 在该示例中，该方法还包括基于分配给当前LCU的比特量来确定当前LCU的量化参数（QP），以及用所确定的QP对当前LCU进行编码。

公开(公告)号：US20140269895A1

公开(公告)日：2014-09-18

申请号：US13801220

申请日：2013-03-13

Applicant: QUALCOMM INCORPORATED

Inventor： Feng Ge ,  Hariharan G. Lalgudi ,  Sumit Mohan ,  Kai Wang ,  Narendranath Malayath

IPC: H04N7/01

CPC classification number: H04N7/0117 ,  H04N19/33 ,  H04N19/42 ,  H04N19/59

Abstract: Implementations include video image processing systems, methods, and apparatus for integrated video downscale in a video core. The downscaler computes and writes a display frame to an external memory. This frame may have the same resolution as a target display device (e.g., mobile device). The target display device then reads this display frame, rather than the original higher resolution frame. By enabling downscale during encoding/decoding, the device can conserve resources such as memory bandwidth, memory access, bus bandwidth, and power consumption associated with separately downscaling a frame of video data.

Abstract translation: 实现包括视频图像处理系统，方法和用于在视频核心中集成视频缩减的装置。 缩放器计算并将显示帧写入外部存储器。 该帧可以具有与目标显示设备（例如，移动设备）相同的分辨率。 目标显示设备然后读取该显示帧，而不是原始的较高分辨率帧。 通过在编码/解码期间实现低档，该设备可以节省与分别缩小视频数据帧相关联的资源，例如存储器带宽，存储器访问，总线带宽和功耗。

公开(公告)号：US20130301727A1

公开(公告)日：2013-11-14

申请号：US13801622

申请日：2013-03-13

Applicant: QUALCOMM INCORPORATED

Inventor： Ling Feng Huang ,  Hari Ganesh Thirunageswaram ,  Hariharan G. Lalgudi ,  Sumit Mohan ,  Kai Wang

IPC: H04N7/26

CPC classification number: H04N19/503 ,  H04N19/102 ,  H04N19/103 ,  H04N19/105 ,  H04N19/136 ,  H04N19/162 ,  H04N19/176 ,  H04N19/50 ,  H04N19/55 ,  H04N19/57 ,  H04N19/593

Abstract: Methods and systems for efficient searching of candidate blocks for inter-coding and/or intra coding are provided. In one innovative aspect, an apparatus for performing motion estimation is provided. The apparatus includes a processor configured to identify a number of candidate blocks of a frame of video data to be searched, at least one candidate block corresponding to a block of another frame of the video data. The processor is further configured to select one or more of the candidate blocks to search based on a distance between the candidate blocks. The processor is also configured to select a method for searching the selected candidate blocks based on a format of the video data. The processor is also configured to estimate the motion for the block of the another frame based on the selected method and the selected candidate blocks.

Abstract translation: 提供了用于有效搜索用于帧间编码和/或帧内编码的候选块的方法和系统。 在一个创新方面，提供了一种用于执行运动估计的装置。 该装置包括：处理器，被配置为识别要搜索的视频数据的帧的候选块的数量;对应于视频数据的另一帧的块的至少一个候选块。 处理器还被配置为基于候选块之间的距离来选择一个或多个候选块进行搜索。 处理器还被配置为基于视频数据的格式来选择用于搜索所选择的候选块的方法。 处理器还被配置为基于所选择的方法和所选择的候选块来估计另一帧的块的运动。

公开(公告)号：US11638020B2

公开(公告)日：2023-04-25

申请号：US17217745

申请日：2021-03-30

Applicant: QUALCOMM Incorporated

Inventor： Yasutomo Matsuba ,  Kai Wang

IPC: H04N19/42 ,  H04N19/107 ,  H04N19/124 ,  H04N19/172 ,  H04N19/18 ,  H04N19/51 ,  H04N19/70

Abstract: A device includes a first bitstream engine and a second bitstream engine. The first bitstream engine is configured to decode a first portion of a first video frame of a plurality of video frames to generate first decoded portion data. The first bitstream engine is also configured to generate synchronization information based on completion of decoding the first portion. The second bitstream engine is configured to, based on the synchronization information, initiate decoding of a second portion of a particular video frame to generate second decoded portion data. The second bitstream engine uses the first decoded portion data during decoding of the second portion of the particular video frame. The particular video frame includes the first video frame or a second video frame of the plurality of video frames.

公开(公告)号：US09762921B2

公开(公告)日：2017-09-12

申请号：US13720499

申请日：2012-12-19

Applicant: QUALCOMM Incorporated

Inventor： Sanjeev Kumar ,  Geert Van der Auwera ,  Kai Wang ,  Shu Xiao ,  Marta Karczewicz

IPC: H04N7/26 ,  H04N19/423 ,  H04N19/80 ,  H04N19/82

CPC classification number: H04N19/423 ,  H04N19/80 ,  H04N19/82

Abstract: An apparatus configured to filter video information according to certain aspects includes a memory unit and a processor in communication with the memory unit. The memory unit stores video information comprising at least two adjacent video blocks, each video block comprising a plurality of video samples, and each video sample having a bit depth. The processor determines a filtered video sample based at least in part on a video sample and an adjustment value. The processor determines the adjustment value at least in part from an input with a limited bit depth. The input is determined from a set of one or more video samples, and its bit depth is limited such that it is less than the bit depth of the one or more video samples.

公开(公告)号：US20170064308A1

公开(公告)日：2017-03-02

申请号：US14839666

申请日：2015-08-28

Applicant: QUALCOMM Incorporated

Inventor： Shu Lin ,  Mang Li ,  Kai Wang ,  Atul Garg

IPC: H04N19/15 ,  H04N19/66 ,  H04N19/88 ,  H04N19/152

CPC classification number: H04N19/15 ,  H04N19/152 ,  H04N19/423 ,  H04N19/433 ,  H04N19/66 ,  H04N19/88

Abstract: Video pixel line buffers are widely used for data processing in video codecs. Video data may be packed into buffers configured to store a plurality of words, each word comprising a series of bits. The video data may be associated with two or more channels. In order to reduce realization costs, data blocks from two different channels may be packed from opposite sides of a word in the buffer in opposite directions. In some embodiments, data blocks from two or more physical channels may be mapped to two or more virtual channels, the virtual channels having balanced data block sizes. The data blocks associated with the virtual channels may then be packed to one or more buffers.

Abstract translation: 视频像素线缓冲器广泛用于视频编解码器中的数据处理。 视频数据可以被打包到被配置为存储多个字的缓冲器中，每个字包括一系列位。 视频数据可以与两个或更多个信道相关联。 为了降低实现成本，来自两个不同通道的数据块可以从相反方向的缓冲器中的字的相对侧打包。 在一些实施例中，来自两个或多个物理信道的数据块可以被映射到两个或更多个虚拟信道，虚拟信道具有平衡的数据块大小。 然后可以将与虚拟通道相关联的数据块打包到一个或多个缓冲器。