Abstract:
Methods and systems for efficient searching of candidate blocks for inter-coding and/or intra coding are provided. In one innovative aspect, an apparatus for performing motion estimation is provided. The apparatus includes a processor configured to identify a number of candidate blocks of a frame of video data to be searched, at least one candidate block corresponding to a block of another frame of the video data. The processor is further configured to select one or more of the candidate blocks to search based on a distance between the candidate blocks. The processor is also configured to select a method for searching the selected candidate blocks based on a format of the video data. The processor is also configured to estimate the motion for the block of the another frame based on the selected method and the selected candidate blocks.
Abstract:
Methods and systems for performing at least one of video encoding and video decoding are disclosed. In one implementation, the system includes a controller configured to determine a video standard associated with a portion of the video data, each portion of the video data associated with one of a plurality of video standards. The controller is further configured to provide a set of the filter parameters which are associated with a video standard to be used for at least one of the video encoding and decoding and at least one filter configured to filter at least one reference pixel received from the reference pixel memory based, at least in part, on the provided set of filter parameters.
Abstract:
Systems and methods for interleaving video sub-blocks in video coding are described herein. In one aspect, an apparatus includes a memory and a video coder. The memory stores a first video block and a second video block. The first video block and the second video block include sub-blocks. The video coder processes a first sub-block of the first video block according to a first process and a second process, and processes a second sub-block of the first video block according to the first process and the second process after processing the first sub-block of the first video block according to the first process and the second process. Further, the video coder processes a first sub-block of the second video block according to the first process before processing the second sub-block of the first video block according to the first process.
Abstract:
Reconfigurable shared memory systems, and related processor-based systems and methods are disclosed. The reconfigurable shared memory system can be included in a processor-based system to provide memory for data storage. In exemplary aspects, the reconfigurable shared memory system not only includes the dedicated memory and the general memory (e.g., system cache memory), but also includes a reconfigurable memory. The reconfigurable memory can be configured as either part of addressable memory space of the dedicated memory if an application requires such additional dedicated memory, and/or configured as part of the addressable memory space of the general memory to provide additional memory to other clients for increased processing performance if such reconfigurable memory is not needed as part of the dedicated memory. The dedicated memory does not have to be sized to the worst-case size requirements of a given application.
Abstract:
In an example, a method for filtering pixel data in video coding comprises determining a pixel filtering task from a plurality of pixel filtering tasks for filtering the pixel data, wherein each filtering task of the plurality of pixel filtering tasks is based on an instruction set for a programmable instruction set based controller, and executing the determined filtering task on the pixel data.
Abstract:
In an example, a method for filtering pixel data in video coding comprises determining a pixel filtering task from a plurality of pixel filtering tasks for filtering the pixel data, wherein each filtering task of the plurality of pixel filtering tasks is based on an instruction set for a programmable instruction set based controller, and executing the determined filtering task on the pixel data.
Abstract:
In some aspects, the present disclosure provides a method for managing a command queue in a universal flash storage (UFS) host device. The method includes determining to power on a first subsystem of a system-on-a-chip (SoC), wherein the determination to power on the first subsystem is made by a second subsystem of the SoC based on detection of user identity data contained in a first image frame during an initial biometric detection process. In certain aspects, the second subsystem is configured to operate independent of the first subsystem and control power to the first subsystem. In certain aspects, the second subsystem includes a second optical sensor, a set of ambient sensors, and a second processor configured to detect, via a set of ambient sensors, an event comprising one or more of an environmental event outside of the device or a motion event of the device.
Abstract:
In some aspects, the present disclosure provides a method for sharing a single optical sensor between multiple image processors. In some embodiments, the method includes receiving, at a control arbiter, a first desired configuration of a first one or more desired configurations for capturing an image frame by the optical sensor, the first one or more desired configurations communicated from a primary image processor. The method may also include receiving, at the control arbiter, a second desired configuration of a second one or more desired configurations for capturing the image frame by the optical sensor, the second one or more desired configurations communicated from a secondary image processor. The method may also include determining, by the control arbiter, an actual configuration for capturing the image frame by the optical sensor, the actual configuration based on the first desired configuration and the second desired configuration.
Abstract:
Methods and systems for performing at least one of video encoding and video decoding are disclosed. In one implementation, the system includes a controller configured to determine a video standard associated with a portion of the video data, each portion of the video data associated with one of a plurality of video standards. The controller is further configured to provide a set of the filter parameters which are associated with a video standard to be used for at least one of the video encoding and decoding and at least one filter configured to filter at least one reference pixel received from the reference pixel memory based, at least in part, on the provided set of filter parameters.
Abstract:
Systems and methods for interleaving video sub-blocks in video coding are described herein. In one aspect, an apparatus includes a memory and a video coder. The memory stores a first video block and a second video block. The first video block and the second video block include sub-blocks. The video coder processes a first sub-block of the first video block according to a first process and a second process, and processes a second sub-block of the first video block according to the first process and the second process after processing the first sub-block of the first video block according to the first process and the second process. Further, the video coder processes a first sub-block of the second video block according to the first process before processing the second sub-block of the first video block according to the first process.