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公开(公告)号：US20170064308A1
公开(公告)日：2017-03-02
申请号：US14839666
申请日：2015-08-28
Applicant: QUALCOMM Incorporated
IPC: H04N19/15 , H04N19/66 , H04N19/88 , H04N19/152
CPC classification number: H04N19/15 , H04N19/152 , H04N19/423 , H04N19/433 , H04N19/66 , H04N19/88
Abstract: Video pixel line buffers are widely used for data processing in video codecs. Video data may be packed into buffers configured to store a plurality of words, each word comprising a series of bits. The video data may be associated with two or more channels. In order to reduce realization costs, data blocks from two different channels may be packed from opposite sides of a word in the buffer in opposite directions. In some embodiments, data blocks from two or more physical channels may be mapped to two or more virtual channels, the virtual channels having balanced data block sizes. The data blocks associated with the virtual channels may then be packed to one or more buffers.
Abstract translation: 视频像素线缓冲器广泛用于视频编解码器中的数据处理。 视频数据可以被打包到被配置为存储多个字的缓冲器中，每个字包括一系列位。 视频数据可以与两个或更多个信道相关联。 为了降低实现成本，来自两个不同通道的数据块可以从相反方向的缓冲器中的字的相对侧打包。 在一些实施例中，来自两个或多个物理信道的数据块可以被映射到两个或更多个虚拟信道，虚拟信道具有平衡的数据块大小。 然后可以将与虚拟通道相关联的数据块打包到一个或多个缓冲器。
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Patent Agency Ranking
公开(公告)号：US20150262328A1
公开(公告)日：2015-09-17
申请号：US14204767
申请日：2014-03-11
Applicant: QUALCOMM Incorporated
Inventor： Shu Lin
CPC classification number: G06T3/40 , G06T3/4007 , G09G2340/0407 , G09G2340/0442 , H04N7/0122
Abstract: Implementations include video image processing systems, methods, and apparatus for downscaling video data using a phase control multi-tap downscale filter. For example, a device configured to process video information may include a memory configured to store a downscaling filter comprising a number of coefficients. A processor may be configured to receive video input data and determine a scale factor between the video input data and a video output. In addition, the processor may be configured to modify the downscaling filter based on the scale factor and the number of coefficients in the unmodified downscaling filter. The processor may be configured to downscale the video input data using the modified downscaling filter.
Abstract translation: 实现包括使用相位控制多抽头低档滤波器来缩小视频数据的视频图像处理系统，方法和装置。 例如，被配置为处理视频信息的设备可以包括被配置为存储包括多个系数的缩减滤波器的存储器。 处理器可以被配置为接收视频输入数据并且确定视频输入数据和视频输出之间的比例因子。 此外，处理器可以被配置为基于缩放因子和未修改的缩小滤波器中的系数数来修改缩小滤波器。 处理器可以被配置为使用修改的缩小滤波器来缩减视频输入数据。
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公开(公告)号：US10277904B2
公开(公告)日：2019-04-30
申请号：US14839666
申请日：2015-08-28
Applicant: QUALCOMM Incorporated
IPC: H04N19/15 , H04N19/152 , H04N19/66 , H04N19/88 , H04N19/423 , H04N19/433
Abstract: Video pixel line buffers are widely used for data processing in video codecs. Video data may be packed into buffers configured to store a plurality of words, each word comprising a series of bits. The video data may be associated with two or more channels. In order to reduce realization costs, data blocks from two different channels may be packed from opposite sides of a word in the buffer in opposite directions. In some embodiments, data blocks from two or more physical channels may be mapped to two or more virtual channels, the virtual channels having balanced data block sizes. The data blocks associated with the virtual channels may then be packed to one or more buffers.
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公开(公告)号：US09275434B2
公开(公告)日：2016-03-01
申请号：US14204767
申请日：2014-03-11
Applicant: QUALCOMM Incorporated
Inventor： Shu Lin
CPC classification number: G06T3/40 , G06T3/4007 , G09G2340/0407 , G09G2340/0442 , H04N7/0122
Abstract: Implementations include video image processing systems, methods, and apparatus for downscaling video data using a phase control multi-tap downscale filter. For example, a device configured to process video information may include a memory configured to store a downscaling filter comprising a number of coefficients. A processor may be configured to receive video input data and determine a scale factor between the video input data and a video output. In addition, the processor may be configured to modify the downscaling filter based on the scale factor and the number of coefficients in the unmodified downscaling filter. The processor may be configured to downscale the video input data using the modified downscaling filter.
Abstract translation: 实现包括使用相位控制多抽头低档滤波器来缩小视频数据的视频图像处理系统，方法和装置。 例如，被配置为处理视频信息的设备可以包括被配置为存储包括多个系数的缩减滤波器的存储器。 处理器可以被配置为接收视频输入数据并且确定视频输入数据和视频输出之间的比例因子。 此外，处理器可以被配置为基于缩放因子和未修改的缩小滤波器中的系数数来修改缩小滤波器。 处理器可以被配置为使用修改的缩小滤波器来缩减视频输入数据。
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公开(公告)号：US20190215518A1
公开(公告)日：2019-07-11
申请号：US15866582
申请日：2018-01-10
Applicant: QUALCOMM Incorporated
Inventor： Aravind Alagappan , Marc Bosch Ruiz , Yu Liu , Shyamprasad Chikkerur , Yunqing Chen , Tushar Singhal , Shu Lin , Kai Wang , Harikrishna Reddy
IPC: H04N19/139 , G06T7/269 , H04N19/53 , G06T7/207
CPC classification number: H04N19/139 , G06T7/207 , G06T7/269 , H04N19/53
Abstract: Methods, systems, and devices for motion analysis are described. Generally, the described techniques provide for computationally efficient and accurate motion analysis. A device may identify frames of a video frame sequence having a defined resolution. The device may downscale the frames to generate a plurality of downsampled images each having a resolution lower than the defined resolution. The device may generate a respective histogram vector for each pixel of each downsampled image and each pixel of the original frames. The device may determine a motion vector candidate based at least in part on the histogram vectors. The device may apply a filter to the motion vector candidates to determine a final motion vector and output an indication of motion between the frames of the video frame sequence based at least in part on the final motion vector for each pixel of the second frame.
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公开(公告)号：US20190174135A1
公开(公告)日：2019-06-06
申请号：US16252231
申请日：2019-01-18
Applicant: QUALCOMM Incorporated
IPC: H04N19/15 , H04N19/433 , H04N19/423 , H04N19/152 , H04N19/66 , H04N19/88
Abstract: Video pixel line buffers are widely used for data processing in video codecs. Video data may be packed into buffers configured to store a plurality of words, each word comprising a series of bits. The video data may be associated with two or more channels. In order to reduce realization costs, data blocks from two different channels may be packed from opposite sides of a word in the buffer in opposite directions. In some embodiments, data blocks from two or more physical channels may be mapped to two or more virtual channels, the virtual channels having balanced data block sizes. The data blocks associated with the virtual channels may then be packed to one or more buffers.
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