Transform hardware architecture for video coding

    公开(公告)号:US10567800B2

    公开(公告)日:2020-02-18

    申请号:US15451944

    申请日:2017-03-07

    IPC分类号: H04N19/61 H04N19/423

    摘要: Techniques are described for performing transformation on video data. A transform circuit may receive M sample values of the video data from a pre-transform buffer, and process the M sample values with N computation units of the transform circuit to generate intermediate values. Processing the M sample values to generate the intermediate values includes feeding back temporary values from output of one or more of the N computation units to input of one or more of the N computation units. The transform circuit may store a first set of the intermediate values in a transpose buffer, and store a second set of the intermediate values in the pre-transform buffer that are to be later retrieved for storage in the transpose buffer.

    TRANSFORM HARDWARE ARCHITECTURE FOR VIDEO CODING

    公开(公告)号:US20180152732A1

    公开(公告)日:2018-05-31

    申请号:US15451944

    申请日:2017-03-07

    IPC分类号: H04N19/61 H04N19/15

    CPC分类号: H04N19/61 H04N19/423

    摘要: Techniques are described for performing transformation on video data. A transform circuit may receive M sample values of the video data from a pre-transform buffer, and process the M sample values with N computation units of the transform circuit to generate intermediate values. Processing the M sample values to generate the intermediate values includes feeding back temporary values from output of one or more of the N computation units to input of one or more of the N computation units. The transform circuit may store a first set of the intermediate values in a transpose buffer, and store a second set of the intermediate values in the pre-transform buffer that are to be later retrieved for storage in the transpose buffer.