Amplifier Configuration for Load-Line Enhancement

    公开(公告)号:US20190097583A1

    公开(公告)日:2019-03-28

    申请号:US16138811

    申请日:2018-09-21

    Inventor: Ibrahim Chamas

    Abstract: Amplifier configuration for load-line enhancement is described herein. In some implementations, an apparatus includes an amplifier. The amplifier includes at least one plus transistor stack, at least one minus transistor stack, and at least one inductor. The at least one plus transistor stack is coupled to a plus amplifier node and a plus input node. The at least one minus transistor stack is coupled to a minus amplifier node and a minus input node. The at least one inductor is coupled between the plus amplifier node and the minus amplifier node, with the at least one inductor including an inter-inductor node. The amplifier also includes a minus power switch coupled between the minus amplifier node and one or more supply voltages and an inductor power switch coupled between the inter-inductor node and at least one supply voltage.

Patent Agency Ranking