公开(公告)号：US20220181325A1

公开(公告)日：2022-06-09

申请号：US17110802

申请日：2020-12-03

Applicant: QUALCOMM Incorporated

Inventor： Harikrishna CHINTARLAPALLI REDDY ,  Pradeep Kumar SANA ,  Chulkyu LEE ,  Jeffrey Charles LEE ,  Sajin MOHAMAD

IPC: H01L27/092 ,  H01L27/02

Abstract: A MOS device includes a set of pMOS transistors on a first side of an IC. The set of pMOS transistors is adjacent to each other in a second direction. The MOS device further includes a set of nMOS transistors on a second side of the IC. The set of nMOS transistors is adjacent to each other in the second direction. The second side is opposite the first side in a first direction orthogonal to the second direction. The MOS device further includes an OD region between the set of pMOS transistors and the set of nMOS transistors. A first set of gate interconnects may extend in the first direction over the OD region. A set of contacts may contact the OD region. The OD region, the first set of gate interconnects, and the set of contacts may form a set of transistors configured as dummy transistors or decoupling capacitors.

公开(公告)号：US20210126819A1

公开(公告)日：2021-04-29

申请号：US17070219

申请日：2020-10-14

Applicant: QUALCOMM Incorporated

Inventor： Chulkyu LEE ,  Ying DUAN ,  Shih-Wei CHOU

IPC: H04L25/49 ,  H04L25/493 ,  H04L25/02 ,  H04L25/14 ,  H04L7/00

Abstract: Methods, apparatus, and systems provide improved throughput on a communication link. An apparatus has a plurality of line drivers, a first wire state encoder configured to receive a first symbol in a sequence of symbols when a 3-wire link is in a first signaling state, and to define a second signaling state for the 3-wire link based on the first symbol and the first signaling state, a second wire state encoder configured to receive a second symbol in the sequence of symbols, and to define a third signaling state for the 3-wire link based on the second symbol and the second signaling state. The first symbol immediately precedes the second symbol in the sequence of symbols. The 3-wire link transitions from the first to the second signaling state, and from the second to the third signaling state in consecutive transmission intervals.

公开(公告)号：US20230221744A1

公开(公告)日：2023-07-13

申请号：US17928174

申请日：2021-04-15

Applicant: QUALCOMM Incorporated

Inventor： Darshan Chandrashekhar PANDE ,  Chulkyu LEE ,  Sajin V MOHAMAD ,  Suresh Naidu LEKKALA

IPC: G05F1/575 ,  H02M3/07

CPC classification number: G05F1/575 ,  H02M3/07

Abstract: In certain aspects, a voltage regulator includes a pass transistor coupled between an input of the voltage regulator and an output of the voltage regulator, and an amplifier having a first input coupled to a reference voltage, a second input coupled to the output of the voltage regulator via a feedback path, and an output. The voltage regulator also includes a voltage booster coupled between the output of the amplifier and a gate of the pass transistor. In certain aspects, the voltage booster includes a first capacitor and a second capacitor for double charge pumping. In certain aspects, a control circuit of the voltage booster is coupled to a voltage source that is independent of an output voltage of the amplifier.

公开(公告)号：US20160013794A1

公开(公告)日：2016-01-14

申请号：US14328671

申请日：2014-07-10

Applicant: QUALCOMM Incorporated

Inventor： Wenjun SU ,  Le ZHANG ,  Chulkyu LEE

IPC: H03K21/00

CPC classification number: H03K21/00 ,  H03K23/483

Abstract: A divide-by-seven divider includes a first module clocked with a clock input, and a second module coupled to the first module and clocked with an output of the first module. The first and second modules are configured to divide the clock input by seven and to output the divided clock input. The first module may be configured to store a count between 0 and 3 in a count cycle. The divide-by-seven divider may further include a feedback module coupled between the first module and the second module that is configured to cause the first module to skip one count in the count between 0 and 3 once every other count cycle. Specifically, the first module may be configured to store incrementally the count “00,” “10,” “11,” and “01” in a count cycle and to skip the count “01” every other count cycle based on input from the feedback module.

Abstract translation: 一个除以七分频器包括以时钟输入为时钟的第一模块，以及耦合到第一模块并与第一模块的输出一起计时的第二模块。 第一和第二模块被配置为将时钟输入除以7并输出分频时钟输入。 第一模块可以被配置为在计数周期中存储0和3之间的计数。 除以七分频器还可以包括耦合在第一模块和第二模块之间的反馈模块，该反馈模块被配置为使得第一模块在每隔一个计数周期之间跳过0和3之间的计数中的一个计数。 具体地，第一模块可以被配置为在计数周期中逐渐地存储计数“00”，“10”，“11”和“01”，并且每隔一个计数周期跳过计数“01”，基于来自 反馈模块

公开(公告)号：US20220158879A1

公开(公告)日：2022-05-19

申请号：US17589083

申请日：2022-01-31

Applicant: QUALCOMM Incorporated

Inventor： Chulkyu LEE ,  Ying DUAN ,  Shih-Wei CHOU

IPC: H04L25/49 ,  H04L25/493 ,  H04L7/00 ,  H04L25/14 ,  H04L25/02

Abstract: Methods, apparatus, and systems provide improved throughput on a communication link. An apparatus has a plurality of line drivers, a first wire state encoder configured to receive a first symbol in a sequence of symbols when a 3-wire link is in a first signaling state, and to define a second signaling state for the 3-wire link based on the first symbol and the first signaling state, a second wire state encoder configured to receive a second symbol in the sequence of symbols, and to define a third signaling state for the 3-wire link based on the second symbol and the second signaling state. The first symbol immediately precedes the second symbol in the sequence of symbols. The 3-wire link transitions from the first to the second signaling state, and from the second to the third signaling state in consecutive transmission intervals.

公开(公告)号：US20210058280A1

公开(公告)日：2021-02-25

申请号：US16984896

申请日：2020-08-04

Applicant: QUALCOMM Incorporated

Inventor： Chulkyu LEE ,  Dhaval SEJPAL ,  George Alan WILEY

IPC: H04L27/20 ,  H04L27/227 ,  H04L27/233

Abstract: Certain disclosed methods, apparatus, and systems enable improved communication on a multiphase communication link through improved encoding techniques and protocol. A data communication apparatus has a plurality of line drivers configured to couple the apparatus to a 3-wire link, and a data encoder configured to encode at least 3 bits of binary data in each transition between two symbols that are consecutively transmitted by the plurality of line drivers over the 3-wire link such that each pair of consecutively-transmitted symbols comprises two different symbols. Each symbol defines signaling states of the 3-wire link during an associated symbol transmission interval such that each wire of the 3-wire link is in a different signaling state from the other wires of the 3-wire link during the associated symbol transmission interval. Data may be encoded using a combination of 3-phase and pulse amplitude modulation.

公开(公告)号：US20210367749A1

公开(公告)日：2021-11-25

申请号：US17307770

申请日：2021-05-04

Applicant: QUALCOMM Incorporated

Inventor： Chulkyu LEE ,  George Alan WILEY

IPC: H04L7/00 ,  H04L12/40 ,  G06F13/42

Abstract: Methods, apparatus, and systems for communication over a C-PHY interface are disclosed. A transmitting device has a driver circuit configured to drive a three-wire bus in accordance with a symbol received at an input of the driver circuit, a pattern detector receives a sequence of symbols to be transmitted over the three-wire bus in a plurality of transmission symbol intervals, and a selection circuit responsive to a select signal provided by the pattern detector and configured to select between delayed and undelayed versions of a current symbol to drive the input of the driver circuit during a corresponding transmission symbol interval. The select signal may select the delayed version of the current symbol when a combination of the current symbol with an immediately preceding symbol cause the pattern detector to indicate a pattern match.

公开(公告)号：US20210297293A1

公开(公告)日：2021-09-23

申请号：US17197335

申请日：2021-03-10

Applicant: QUALCOMM Incorporated

Inventor： Chulkyu LEE ,  Hyunjeong PARK

IPC: H04L25/02 ,  G06F13/40 ,  H04L25/03

Abstract: A termination for a high-frequency transmission line includes a first resistor that has a first terminal coupled to a first end of a transmission line and a second terminal coupled to a first input/output pad, and a second resistor that has a first terminal coupled to the first input/output pad. The first resistor and the second resistor may provide a combined resistance that matches a nominal value of a characteristic impedance of the transmission line. The apparatus may include a third resistor having a first terminal coupled to a second end of a transmission line, and a second terminal coupled to a second input/output pad, and a fourth resistor having a first terminal coupled to the second input/output pad. The third resistor and the fourth resistor may provide a combined resistance that matches the nominal value of the characteristic impedance of the transmission line.

公开(公告)号：US20190356519A1

公开(公告)日：2019-11-21

申请号：US16526332

申请日：2019-07-30

Applicant: QUALCOMM Incorporated

Inventor： Shih-Wei CHOU ,  Chulkyu LEE ,  Dhaval SEJPAL

IPC: H04L25/493 ,  H04L25/02

Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within electronic equipment. Transmission lines are selectively terminated in an N-phase polarity encoded transmitter when the transmission lines would otherwise be undriven. Data is mapped to a sequence of symbols to be transmitted on a plurality of wires. The sequence of symbols is encoded in three signals. A first terminal of a plurality of terminals may be driven such that transistors are activated to couple the first terminal to first and second voltage levels. The first terminal may further be driven such that a dedicated transistor is activated to couple the first terminal to an intermediate voltage level.

公开(公告)号：US20180337698A1

公开(公告)日：2018-11-22

申请号：US16050603

申请日：2018-07-31

Applicant: QUALCOMM Incorporated

Inventor： Shih-Wei CHOU ,  Chulkyu LEE ,  Dhaval SEJPAL

IPC: H04B1/04 ,  H04L25/493 ,  H04L25/02 ,  G06F13/40 ,  H04B3/52

CPC classification number: H04L25/493 ,  H04L25/02 ,  H04L25/0276

Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within electronic equipment. Transmission lines are selectively terminated in an N-phase polarity encoded transmitter when the transmission lines would otherwise be undriven. Data is mapped to a sequence of symbols to be transmitted on a plurality of wires. The sequence of symbols is encoded in three signals. A first terminal of a plurality of terminals may be driven such that transistors are activated to couple the first terminal to first and second voltage levels. The first terminal may further be driven such that a dedicated transistor is activated to couple the first terminal to an intermediate voltage level.