公开(公告)号：US20160013794A1

公开(公告)日：2016-01-14

申请号：US14328671

申请日：2014-07-10

Applicant: QUALCOMM Incorporated

Inventor： Wenjun SU ,  Le ZHANG ,  Chulkyu LEE

IPC: H03K21/00

CPC classification number: H03K21/00 ,  H03K23/483

Abstract: A divide-by-seven divider includes a first module clocked with a clock input, and a second module coupled to the first module and clocked with an output of the first module. The first and second modules are configured to divide the clock input by seven and to output the divided clock input. The first module may be configured to store a count between 0 and 3 in a count cycle. The divide-by-seven divider may further include a feedback module coupled between the first module and the second module that is configured to cause the first module to skip one count in the count between 0 and 3 once every other count cycle. Specifically, the first module may be configured to store incrementally the count “00,” “10,” “11,” and “01” in a count cycle and to skip the count “01” every other count cycle based on input from the feedback module.

Abstract translation: 一个除以七分频器包括以时钟输入为时钟的第一模块，以及耦合到第一模块并与第一模块的输出一起计时的第二模块。 第一和第二模块被配置为将时钟输入除以7并输出分频时钟输入。 第一模块可以被配置为在计数周期中存储0和3之间的计数。 除以七分频器还可以包括耦合在第一模块和第二模块之间的反馈模块，该反馈模块被配置为使得第一模块在每隔一个计数周期之间跳过0和3之间的计数中的一个计数。 具体地，第一模块可以被配置为在计数周期中逐渐地存储计数“00”，“10”，“11”和“01”，并且每隔一个计数周期跳过计数“01”，基于来自 反馈模块