公开(公告)号：US20230396248A1

公开(公告)日：2023-12-07

申请号：US18336621

申请日：2023-06-16

Applicant: QUALCOMM Incorporated

Inventor： Abhinav MURALI ,  Pradeep Kumar SANA ,  Sajin MOHAMAD ,  Harikrishna CHINTARLAPALLI REDDY ,  Rakesh Kumar SINHA ,  Jibu VARGHESE K

IPC: H03K17/687 ,  H04B1/40

CPC classification number: H03K17/6872 ,  H04B1/40

Abstract: An integrated circuit (IC), including: a current mirror, including: a first field effect transistor (FET) including a first drain, a first gate, and a first source, wherein the first source is coupled to a first voltage rail; and a second FET including a second drain, a second gate, and a second source, wherein the second gate is coupled to the first gate of the first FET, and the second source is coupled to the first voltage rail; and a selective coupling circuit configured to selectively couple the first drain of the first FET to the first and second gates of the first and second FETs based on a voltage at the first drain of the first FET.

公开(公告)号：US20220181325A1

公开(公告)日：2022-06-09

申请号：US17110802

申请日：2020-12-03

Applicant: QUALCOMM Incorporated

Inventor： Harikrishna CHINTARLAPALLI REDDY ,  Pradeep Kumar SANA ,  Chulkyu LEE ,  Jeffrey Charles LEE ,  Sajin MOHAMAD

IPC: H01L27/092 ,  H01L27/02

Abstract: A MOS device includes a set of pMOS transistors on a first side of an IC. The set of pMOS transistors is adjacent to each other in a second direction. The MOS device further includes a set of nMOS transistors on a second side of the IC. The set of nMOS transistors is adjacent to each other in the second direction. The second side is opposite the first side in a first direction orthogonal to the second direction. The MOS device further includes an OD region between the set of pMOS transistors and the set of nMOS transistors. A first set of gate interconnects may extend in the first direction over the OD region. A set of contacts may contact the OD region. The OD region, the first set of gate interconnects, and the set of contacts may form a set of transistors configured as dummy transistors or decoupling capacitors.