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    C-PHY HALF-RATE WIRE STATE ENCODER AND DECODER
    2.
    发明申请
    C-PHY HALF-RATE WIRE STATE ENCODER AND DECODER 有权

    公开(公告)号：US20220158879A1

    公开(公告)日：2022-05-19

    申请号：US17589083

    申请日：2022-01-31

    Applicant: QUALCOMM Incorporated

    Inventor： Chulkyu LEE ,  Ying DUAN ,  Shih-Wei CHOU

    IPC: H04L25/49 ,  H04L25/493 ,  H04L7/00 ,  H04L25/14 ,  H04L25/02

    Abstract: Methods, apparatus, and systems provide improved throughput on a communication link. An apparatus has a plurality of line drivers, a first wire state encoder configured to receive a first symbol in a sequence of symbols when a 3-wire link is in a first signaling state, and to define a second signaling state for the 3-wire link based on the first symbol and the first signaling state, a second wire state encoder configured to receive a second symbol in the sequence of symbols, and to define a third signaling state for the 3-wire link based on the second symbol and the second signaling state. The first symbol immediately precedes the second symbol in the sequence of symbols. The 3-wire link transitions from the first to the second signaling state, and from the second to the third signaling state in consecutive transmission intervals.

    C-PHY RECEIVER WITH SELF-REGULATED COMMON MODE SERVO LOOP
    3.
    发明申请
    C-PHY RECEIVER WITH SELF-REGULATED COMMON MODE SERVO LOOP 有权

    公开(公告)号：US20230087897A1

    公开(公告)日：2023-03-23

    申请号：US17483142

    申请日：2021-09-23

    Applicant: QUALCOMM Incorporated

    Inventor： Shih-Wei CHOU ,  Todd Morgan RASMUS ,  Ying DUAN ,  Abhay DIXIT

    IPC: H04L12/40 ,  H03F3/19 ,  H04B1/16 ,  H04L29/08

    Abstract: A receiving apparatus includes a terminating network for a three-wire serial bus and a feedback circuit. Each wire of the three-wire serial bus may be coupled through a resistance to a common node of the terminating network. The feedback circuit has a first amplifier circuit having an input coupled to the common node, a comparator that receives an output of the first amplifier circuit as a first input and a reference voltage as a second input, and a second amplifier circuit responsive to an output of the comparator and configured to inject a current through the common node.

    C-PHY HALF-RATE WIRE STATE ENCODER AND DECODER
    4.
    发明申请
    C-PHY HALF-RATE WIRE STATE ENCODER AND DECODER 有权

    公开(公告)号：US20210126819A1

    公开(公告)日：2021-04-29

    申请号：US17070219

    申请日：2020-10-14

    Applicant: QUALCOMM Incorporated

    Inventor： Chulkyu LEE ,  Ying DUAN ,  Shih-Wei CHOU

    IPC: H04L25/49 ,  H04L25/493 ,  H04L25/02 ,  H04L25/14 ,  H04L7/00

    Abstract: Methods, apparatus, and systems provide improved throughput on a communication link. An apparatus has a plurality of line drivers, a first wire state encoder configured to receive a first symbol in a sequence of symbols when a 3-wire link is in a first signaling state, and to define a second signaling state for the 3-wire link based on the first symbol and the first signaling state, a second wire state encoder configured to receive a second symbol in the sequence of symbols, and to define a third signaling state for the 3-wire link based on the second symbol and the second signaling state. The first symbol immediately precedes the second symbol in the sequence of symbols. The 3-wire link transitions from the first to the second signaling state, and from the second to the third signaling state in consecutive transmission intervals.

    MIPI D-PHY RECEIVER AUTO RATE DETECTION AND HIGH-SPEED SETTLE TIME CONTROL
    5.
    发明申请
    MIPI D-PHY RECEIVER AUTO RATE DETECTION AND HIGH-SPEED SETTLE TIME CONTROL 有权

    公开(公告)号：US20210103547A1

    公开(公告)日：2021-04-08

    申请号：US16591719

    申请日：2019-10-03

    Applicant: QUALCOMM Incorporated

    Inventor： Yasser AHMED ,  Ying DUAN ,  Shih-Wei CHOU

    IPC: G06F13/42

    Abstract: System, methods and apparatus are described that support multimode operation of a data communication interface. An apparatus includes a physical layer interface coupled to a serial bus and configurable for a high-speed mode of communication and a low-speed mode of communication, and a rate detector configured to receive a clock signal from the serial bus, and to use a reference clock to determine a unit interval representative of a data rate of the serial bus. The apparatus may also include interval calculation logic configured to determine an interval related to timing of a data signal transmitted on the serial bus, the interval having a duration expressed as a number of cycles of the reference clock. The physical layer interface may be configured to use the interval to capture data in the data signal.

    SMALL LOOP DELAY CLOCK AND DATA RECOVERY BLOCK FOR HIGH-SPEED NEXT GENERATION C-PHY
    6.
    发明申请
    SMALL LOOP DELAY CLOCK AND DATA RECOVERY BLOCK FOR HIGH-SPEED NEXT GENERATION C-PHY 有权

    公开(公告)号：US20210336760A1

    公开(公告)日：2021-10-28

    申请号：US17305542

    申请日：2021-07-09

    Applicant: QUALCOMM Incorporated

    Inventor： Ying DUAN ,  Jing WU ,  Shih-Wei CHOU

    IPC: H04L7/00

    Abstract: Methods, apparatus, and systems for communication over a multi-wire, multi-phase interface are disclosed. A clock recovery method includes generating a combination signal that includes transition pulses, each transition pulse being generated responsive to a transition in a difference signal representative of a difference in signaling state of a pair of wires in a three-wire bus. The combination signal is provided to a logic circuit that is configured to provide a clock signal as its output, where pulses in the combination signal cause the clock signal to be driven to a first state. The logic circuit receives a reset signal that is derived from the clock signal by delaying transitions to the first state while passing transitions from the first state without added delay. The clock signal is driven from the first state after passing a transition of the clock signal to the first state.

    OPEN-LOOP, SUPER FAST, HALF-RATE CLOCK AND DATA RECOVERY FOR NEXT GENERATION C-PHY INTERFACES
    7.
    发明申请
    OPEN-LOOP, SUPER FAST, HALF-RATE CLOCK AND DATA RECOVERY FOR NEXT GENERATION C-PHY INTERFACES 有权

    公开(公告)号：US20210184829A1

    公开(公告)日：2021-06-17

    申请号：US16711230

    申请日：2019-12-11

    Applicant: QUALCOMM Incorporated

    Inventor： Ying DUAN ,  Abhay DIXIT ,  Shih-Wei CHOU

    IPC: H04L7/033 ,  H04L7/00

    Abstract: Methods, apparatus, and systems for communication over a multi-wire, multi-phase interface are disclosed. A clock recovery apparatus has a plurality of pulse generating circuits, a logic circuit and a delay flipflop. Each pulse generating circuit generates transition pulses in response to transitions in one of three difference signals representative of a difference in signaling state of a pair of wires in a three-wire bus. Transitions in the difference signals can occur at boundaries between sequentially-transmitted symbols. The first logic circuit may provide a single pulse in a combination signal at each boundary between pairs of symbols by combining one or more transition pulses. The delay flipflop is configured to respond to each pulse in the combination signal by changing signaling state of a clock signal that is output by the clock recovery apparatus. The symbols may be sequentially transmitted over the three-wire bus in accordance with a C-PHY protocol.

    SMALL LOOP DELAY CLOCK AND DATA RECOVERY BLOCK FOR HIGH-SPEED NEXT GENERATION C-PHY
    8.
    发明申请
    SMALL LOOP DELAY CLOCK AND DATA RECOVERY BLOCK FOR HIGH-SPEED NEXT GENERATION C-PHY 有权

    公开(公告)号：US20210126765A1

    公开(公告)日：2021-04-29

    申请号：US17001801

    申请日：2020-08-25

    Applicant: QUALCOMM Incorporated

    Inventor： Ying DUAN ,  Jing WU ,  Shih-Wei CHOU

    IPC: H04L7/00

    Abstract: Methods, apparatus, and systems for communication over a multi-wire, multi-phase interface are disclosed. A clock recovery method includes generating a combination signal that includes transition pulses, each transition pulse being generated responsive to a transition in a difference signal representative of a difference in signaling state of a pair of wires in a three-wire bus. The combination signal is provided to a logic circuit that is configured to provide a clock signal as its output, where pulses in the combination signal cause the clock signal to be driven to a first state. The logic circuit receives a reset signal that is derived from the clock signal by delaying transitions to the first state while passing transitions from the first state without added delay. The clock signal is driven from the first state after passing a transition of the clock signal to the first state.

    RADIO FREQUENCY INTERFERENCE COMMON MODE INJECTION IN A C-PHY RECEIVER
    9.
    发明申请
    RADIO FREQUENCY INTERFERENCE COMMON MODE INJECTION IN A C-PHY RECEIVER 有权

    公开(公告)号：US20250077462A1

    公开(公告)日：2025-03-06

    申请号：US18462107

    申请日：2023-09-06

    Applicant: QUALCOMM Incorporated

    Inventor： Panchami DEVASHYA SHIVARAMA ,  Ying DUAN ,  Qinqing CAO ,  Seuk SON ,  Mansoor Basha SHAIK ,  Abhay DIXIT

    IPC: G06F13/42 ,  G06F13/40

    Abstract: An input buffer includes a pair of input transistors and associated injection circuits. A first input transistor has a source coupled to a first voltage rail through a first current source and a gate coupled to a first wire of a multi-wire serial bus. Three or more resistors in a first injection circuit couple the wires of the serial bus to a first common node, which is coupled to the source of the first input transistor by a first capacitor. A second input transistor has a source coupled to the first voltage rail through a second current source and a gate coupled to a second wire of the serial bus. Three or more resistors in a second injection circuit couple the wires of the multi-wire serial bus to a second common node, which is coupled to the source of the second input transistor by a second capacitor.

    COMPENSATION OF COMMON MODE VOLTAGE DROP OF SENSING AMPLIFIER OUTPUT DUE TO DECISION FEEDBACK EQUALIZER (DFE) TAPS
    10.
    发明申请
    COMPENSATION OF COMMON MODE VOLTAGE DROP OF SENSING AMPLIFIER OUTPUT DUE TO DECISION FEEDBACK EQUALIZER (DFE) TAPS 有权

    公开(公告)号：US20220077830A1

    公开(公告)日：2022-03-10

    申请号：US17017239

    申请日：2020-09-10

    Applicant: QUALCOMM Incorporated

    Inventor： Ying DUAN ,  Jing WU ,  Zhi ZHU

    IPC: H03F3/45 ,  H03K5/24 ,  H03K3/037 ,  H04L25/03

    Abstract: A receiver including a first differential sense amplifier configured to amplify an input differential data signal to generate an output differential data signal; a first set of one or more differential decision feedback equalizer (DFE) taps configured to modify the output differential data signal based on a set of one or more differential tap signals, wherein the first set of one or more differential DFE taps affect an output common mode voltage associated with the output differential data signal; and a compensation circuit configured to adjusts the output common mode voltage to compensate for the effect on the output common mode voltage by the set of one or more differential DFE taps. The compensation circuit includes reference and replica receivers to generate reference and replica output common mode voltages, and a feedback circuit to adjust the output common mode voltage based on the reference and replica output common mode voltages.

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