公开(公告)号：US20210058280A1

公开(公告)日：2021-02-25

申请号：US16984896

申请日：2020-08-04

Applicant: QUALCOMM Incorporated

Inventor： Chulkyu LEE ,  Dhaval SEJPAL ,  George Alan WILEY

IPC: H04L27/20 ,  H04L27/227 ,  H04L27/233

Abstract: Certain disclosed methods, apparatus, and systems enable improved communication on a multiphase communication link through improved encoding techniques and protocol. A data communication apparatus has a plurality of line drivers configured to couple the apparatus to a 3-wire link, and a data encoder configured to encode at least 3 bits of binary data in each transition between two symbols that are consecutively transmitted by the plurality of line drivers over the 3-wire link such that each pair of consecutively-transmitted symbols comprises two different symbols. Each symbol defines signaling states of the 3-wire link during an associated symbol transmission interval such that each wire of the 3-wire link is in a different signaling state from the other wires of the 3-wire link during the associated symbol transmission interval. Data may be encoded using a combination of 3-phase and pulse amplitude modulation.

公开(公告)号：US20190266119A1

公开(公告)日：2019-08-29

申请号：US16230317

申请日：2018-12-21

Applicant: QUALCOMM Incorporated

Inventor： George Alan WILEY

IPC: G06F13/40 ,  G06F13/20

Abstract: System, methods and apparatus are described that support multimode operation of a data communication interface. A method performed in a device coupled to a multi-wire bus includes configuring a bus interface to drive the multi-wire bus in a high-speed mode, transmitting a plurality of symbols over the multi-wire bus while the bus interface is configured to drive the multi-wire bus in the high-speed mode, providing a control sequence of symbols in the plurality of symbols, and configuring the bus interface to operate as a receiver in the high-speed mode when the control code comprises a turnaround code. The first data may be encoded in the plurality of symbols. The control sequence of symbols may include a control code that is transmitted between two synchronizing sequences of symbols.

公开(公告)号：US20190097852A1

公开(公告)日：2019-03-28

申请号：US16128348

申请日：2018-09-11

Applicant: QUALCOMM Incorporated

Inventor： George Alan WILEY

IPC: H04L27/20 ,  H04L25/02

CPC classification number: H04L27/2057 ,  H04L25/0272 ,  H04L25/49

Abstract: Systems, methods and apparatus are described that facilitate transmission of data between two devices within an electronic apparatus. An apparatus has a bus interface, a 3-phase encoder, and a processing circuit that can configure the 3-phase encoder for a first mode of operation in which data is encoded in a sequence of two-bit symbols, transmit a first three-phase signal representative of the sequence of two-bit symbols on each of the three wires. The processing circuit may be configured to configure the 3-phase encoder for a second mode of operation in which data is encoded in a sequence of three-bit symbols. Three-phase signal representative of the sequence of two-bit symbols or sequence of three-bit symbols on each of three wires, where a three-phase signal is in a different phase on each wire when transmitted, and a transition in signaling state occurs between transmission of each pair of symbols.

公开(公告)号：US20210367749A1

公开(公告)日：2021-11-25

申请号：US17307770

申请日：2021-05-04

Applicant: QUALCOMM Incorporated

Inventor： Chulkyu LEE ,  George Alan WILEY

IPC: H04L7/00 ,  H04L12/40 ,  G06F13/42

Abstract: Methods, apparatus, and systems for communication over a C-PHY interface are disclosed. A transmitting device has a driver circuit configured to drive a three-wire bus in accordance with a symbol received at an input of the driver circuit, a pattern detector receives a sequence of symbols to be transmitted over the three-wire bus in a plurality of transmission symbol intervals, and a selection circuit responsive to a select signal provided by the pattern detector and configured to select between delayed and undelayed versions of a current symbol to drive the input of the driver circuit during a corresponding transmission symbol interval. The select signal may select the delayed version of the current symbol when a combination of the current symbol with an immediately preceding symbol cause the pattern detector to indicate a pattern match.

公开(公告)号：US20180006851A1

公开(公告)日：2018-01-04

申请号：US15703878

申请日：2017-09-13

Applicant: QUALCOMM Incorporated

Inventor： George Alan WILEY

IPC: H04L25/49 ,  H04L5/20 ,  H04L27/22 ,  H04L7/033 ,  H04L25/02

CPC classification number: H04L25/4917 ,  H04L5/20 ,  H04L7/033 ,  H04L25/0272 ,  H04L25/0282 ,  H04L25/0294 ,  H04L25/0298 ,  H04L27/22

Abstract: A high-speed serial interface is provided. In one aspect, the high-speed serial interface uses three phase modulation for jointly encoding data and clock information. Accordingly, the need for de-skewing circuitry at the receiving end of the interface is eliminated, resulting in reduced link start-up time and improved link efficiency and power consumption. In one embodiment, the high-speed serial interface uses fewer signal conductors than conventional systems having separate conductors for data and clock information. In another embodiment, the serial interface allows for data to be transmitted at any speed without the receiving end having prior knowledge of the transmission data rate. In another aspect, the high-speed serial interface uses polarity encoded three phase modulation for jointly encoding data and clock information. This further increases the link capacity of the serial interface by allowing for more than one bit to be transmitted in any single baud interval.

公开(公告)号：US20170039929A1

公开(公告)日：2017-02-09

申请号：US14818675

申请日：2015-08-05

Applicant: QUALCOMM Incorporated

Inventor： George Alan WILEY

IPC: G09G3/20 ,  G09G5/00

CPC classification number: G09G3/2092 ,  G06F3/0412 ,  G06F13/4072 ,  G09G3/20 ,  G09G5/008 ,  G09G2300/0426 ,  G09G2300/043 ,  G09G2300/0809 ,  G09G2310/08 ,  G09G2320/0209 ,  G09G2320/0223 ,  G09G2370/00 ,  H04L25/0274 ,  H04L25/0278 ,  H04L25/03

Abstract: A termination circuit can include an impedance component. A first port can be configured to be connected to a first node. The first node can be a node of a conductor of a cable. A first end of the cable can be configured to be connected to a signal producing circuit. A second end of the cable can be configured to be connected to a first end of a trace disposed on a substrate of a display device. A second end of the trace can be connected to a display driver integrated circuit (DDIC). The DDIC can lack a termination impedance component internal to the DDIC to provide a line termination function for a serial interface with the signal producing circuit. A second port can be configured to be connected to a second node. The impedance component can be connected between the first port and the second port.

Abstract translation: 终端电路可以包括阻抗分量。 第一个端口可以配置为连接到第一个节点。 第一节点可以是电缆导体的节点。 电缆的第一端可被配置为连接到信号产生电路。 电缆的第二端可以被配置为连接到布置在显示装置的基板上的迹线的第一端。 迹线的第二端可以连接到显示驱动器集成电路（DDIC）。 DDIC可能缺少DDIC内部的终端阻抗分量，为信号产生电路的串行接口提供线路终端功能。 可以将第二端口配置为连接到第二节点。 阻抗部件可以连接在第一端口和第二端口之间。