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    NON-VOLATILE RANDOM ACCESS MEMORY WITH GATED SECURITY ACCESS
    1.
    发明申请
    NON-VOLATILE RANDOM ACCESS MEMORY WITH GATED SECURITY ACCESS 审中-公开

    公开(公告)号：US20180189195A1

    公开(公告)日：2018-07-05

    申请号：US15399625

    申请日：2017-01-05

    Applicant: QUALCOMM INCORPORATED

    Inventor： DEXTER CHUN ,  YANRU LI

    IPC: G06F12/14 ,  G06F21/60

    CPC classification number: G06F12/1425 ,  G06F21/602 ,  G06F21/79 ,  G06F2212/1052

    Abstract: Systems and methods are disclosed for providing secure access to a non-volatile random access memory. One such method comprises sending an unlock password to a non-volatile random access memory (NVRAM) in response to a trusted boot program executing on a system on chip (SoC). The NVRAM compares the unlock password to a pass gate value provisioned in the NVRAM. If the unlock password matches the pass gate value, a pass gate is unlocked to enable the SoC to access a non-volatile cell array in the NVRAM.

    SYSTEM AND METHOD FOR MEMORY CHANNEL INTERLEAVING WITH SELECTIVE POWER OR PERFORMANCE OPTIMIZATION
    3.
    发明申请
    SYSTEM AND METHOD FOR MEMORY CHANNEL INTERLEAVING WITH SELECTIVE POWER OR PERFORMANCE OPTIMIZATION 有权
    用于存储通道交换的系统和方法，具有选择性或性能优化

    公开(公告)号：US20150046732A1

    公开(公告)日：2015-02-12

    申请号：US13962746

    申请日：2013-08-08

    Applicant: QUALCOMM INCORPORATED

    Inventor： DEXTER CHUN ,  YANRU LI ,  ALEX TU ,  MICHAEL LO

    IPC: G06F1/32 ,  G11C14/00 ,  G06F12/06

    CPC classification number: G06F1/3275 ,  G06F12/0607 ,  G06F2212/1028 ,  G11C14/0009 ,  Y02D10/13 ,  Y02D10/14

    Abstract: Systems and methods are disclosed for providing memory channel interleaving with selective power or performance optimization. One such method involves configuring a memory address map for two or more memory devices accessed via two or more respective memory channels with an interleaved region and a linear region. The interleaved region comprises an interleaved address space for relatively higher performance use cases. The linear region comprises a linear address space for relatively lower power use cases. Memory requests are received from one or more clients. The memory requests comprise a preference for power savings or performance. Received memory requests are assigned to the linear region or the interleaved region according to the preference for power savings or performance.

    Abstract translation: 公开了用于提供具有选择性功率或性能优化的存储器通道交织的系统和方法。 一种这样的方法涉及为经由具有交织区域和线性区域的两个或多个相应存储器通道访问的两个或多个存储器件配置存储器地址映射。 交织区域包括用于相对较高性能使用情况的交织地址空间。 线性区域包括用于相对较低功率使用情况的线性地址空间。 从一个或多个客户端收到内存请求。 存储器请求包括对节能或性能的偏好。 根据对功率节省或性能的偏好，接收到的存储器请求被分配给线性区域或交织区域。

    SYSTEMS AND METHODS FOR REDUCING MEMORY POWER CONSUMPTION VIA PRE-FILLED DRAM VALUES
    4.
    发明申请
    SYSTEMS AND METHODS FOR REDUCING MEMORY POWER CONSUMPTION VIA PRE-FILLED DRAM VALUES 审中-公开

    公开(公告)号：US20180286473A1

    公开(公告)日：2018-10-04

    申请号：US15472622

    申请日：2017-03-29

    Applicant: QUALCOMM INCORPORATED

    Inventor： DEXTER CHUN ,  YANRU LI

    IPC: G11C11/4091 ,  G11C11/4093 ,  G11C11/4096

    Abstract: Systems and methods are disclosed for reducing memory power consumption via pre-filled dynamic random access memory (DRAM) values. One embodiment is a method for providing DRAM values. A fill request is received from an executing program to fill an allocated portion of the DRAM with a predetermined pattern of values. The predetermined pattern of values is stored in a fill value memory residing in the DRAM. A fill command is sent to the DRAM. In response to the fill command, a plurality of sense amp latches are connected to the fill value memory to update the corresponding sense amp latch bits with the predetermined pattern of values stored in the fill value memory.

    System and Method for Sharing a Solid-State Non-Volatile Memory Resource
    7.
    发明申请
    System and Method for Sharing a Solid-State Non-Volatile Memory Resource 审中-公开
    用于共享固态非易失性存储器资源的系统和方法

    公开(公告)号：US20160077959A1

    公开(公告)日：2016-03-17

    申请号：US14485555

    申请日：2014-09-12

    Applicant: Qualcomm Incorporated

    Inventor： NHON TOAI QUACH ,  YANRU LI ,  WILLIAM EDWARD KIMBERLY

    IPC: G06F12/02

    CPC classification number: G06F12/0246 ,  G06F3/0625 ,  G06F3/0659 ,  G06F3/0679 ,  G06F9/4401 ,  G06F12/0284 ,  Y02D10/154

    Abstract: A computing device and methods for exposing a solid-state non-volatile memory element to multiple masters in a computing device are disclosed. A portion of a solid-state non-volatile memory element includes code and data for use by a non-boot processing resource. A host controller in communication with the solid-state non-volatile memory element is modified to receive and respond to a resource identifier unique to the processing resource that is requesting read access to the solid-state non-volatile memory element. Logic executed by a boot master and logic executed by a non-boot processing resource are synchronized in response to a set of indicators.

    Abstract translation: 公开了一种用于将固态非易失性存储元件暴露于计算设备中的多个主器件的计算设备和方法。 固态非易失性存储元件的一部分包括由非引导处理资源使用的代码和数据。 与固态非易失性存储器元件通信的主机控制器被修改为接收和响应正在请求对固态非易失性存储器元件的读访问的处理资源唯一的资源标识符。 由引导主机执行的逻辑和由非引导处理资源执行的逻辑被响应于一组指示符而被同步。

    SYSTEMS AND METHODS FOR EXPANDING MEMORY FOR A SYSTEM ON CHIP
    8.
    发明申请
    SYSTEMS AND METHODS FOR EXPANDING MEMORY FOR A SYSTEM ON CHIP 有权
    用于扩展芯片系统的存储器的系统和方法

    公开(公告)号：US20160054928A1

    公开(公告)日：2016-02-25

    申请号：US14464598

    申请日：2014-08-20

    Applicant: QUALCOMM INCORPORATED

    Inventor： DEXTER TAMIO CHUN ,  SURYANARAYANA CHINA CHITTULURI ,  YANRU LI

    IPC: G06F3/06 ,  G06F12/10

    CPC classification number: G06F3/0607 ,  G06F3/0631 ,  G06F3/0665 ,  G06F3/0683 ,  G06F12/0246 ,  G06F12/06 ,  G06F12/10 ,  G06F13/1684 ,  G06F2212/1048 ,  G06F2212/152 ,  G06F2212/171 ,  G06F2212/206 ,  G06F2212/214 ,  G06F2212/261 ,  G06F2212/654 ,  G06F2212/7201

    Abstract: Systems and methods are disclosed for expanding memory for a system on chip (SoC). A memory card is loaded in an expandable memory socket electrically and is coupled to a system on chip (SoC) via an expansion bus. The memory card comprises a first volatile memory device. In response to detecting the memory card, an expanded virtual memory map is configured. The expanded virtual memory map comprises a first virtual memory space associated the first volatile memory device and a second virtual memory space associated with a second volatile memory device electrically coupled to the SoC via a memory bus. One or more peripheral images associated with the second virtual memory space are relocated to a first portion of the first virtual memory space. A second portion of the first virtual memory space is configured as a block device for performing swap operations associated with the second virtual memory space.

    Abstract translation: 公开了用于扩展片上系统（SoC）的存储器的系统和方法。 存储卡电气地装载在可扩展存储器插槽中，并通过扩展总线耦合到片上系统（SoC）。 存储卡包括第一易失性存储器件。 响应于检测到存储卡，配置扩展的虚拟存储器映射。 扩展的虚拟存储器映射包括与第一易失性存储器设备相关联的第一虚拟存储器空间和与经由存储器总线电耦合到SoC的第二易失性存储器设备相关联的第二虚拟存储器空间。 与第二虚拟存储器空间相关联的一个或多个周边图像被重新定位到第一虚拟存储器空间的第一部分。 第一虚拟存储器空间的第二部分被配置为用于执行与第二虚拟存储器空间相关联的交换操作的块设备。

    SYSTEM AND METHOD FOR PAGE-BY-PAGE MEMORY CHANNEL INTERLEAVING
    9.
    发明申请
    SYSTEM AND METHOD FOR PAGE-BY-PAGE MEMORY CHANNEL INTERLEAVING 审中-公开

    公开(公告)号：US20170108911A1

    公开(公告)日：2017-04-20

    申请号：US14885793

    申请日：2015-10-16

    Applicant: QUALCOMM INCORPORATED

    Inventor： DEXTER TAMIO CHUN ,  YANRU LI

    IPC: G06F1/32 ,  G06F12/10

    CPC classification number: G06F1/324 ,  G06F1/3275 ,  G06F3/0625 ,  G06F12/0607 ,  G06F12/10 ,  G06F12/1009 ,  G06F2212/1016 ,  G06F2212/1028 ,  Y02D10/13

    Abstract: Systems and methods are disclosed for providing memory channel interleaving with selective power or performance optimization. One such method comprises configuring a memory address map for two or more memory devices accessed via two or more respective memory channels with an interleaved region and a linear region. The interleaved region comprises an interleaved address space for relatively higher performance tasks. The linear region comprises a linear address space for relatively lower power tasks. A request is received from a process for a virtual memory page. The request comprises a preference for power savings or performance. The virtual memory page is assigned to a free physical page in the linear region or the interleaved region according to the preference for power savings or performance.

    SCHEDULING VOLATILE MEMORY MAINTENANCE EVENTS IN A MULTI-PROCESSOR SYSTEM
    10.
    发明申请
    SCHEDULING VOLATILE MEMORY MAINTENANCE EVENTS IN A MULTI-PROCESSOR SYSTEM 审中-公开
    在多处理器系统中调度挥发性记忆维护事件

    公开(公告)号：US20160239442A1

    公开(公告)日：2016-08-18

    申请号：US14622017

    申请日：2015-02-13

    Applicant: QUALCOMM INCORPORATED

    Inventor： DEXTER TAMIO CHUN ,  YANRU LI ,  RICHARD ALAN STEWART ,  SUBRATO KUMAR DE

    IPC: G06F13/26 ,  G06F13/18

    CPC classification number: G06F13/26 ,  G06F13/1636 ,  G06F13/1663 ,  G06F13/18

    Abstract: Systems, methods, and computer programs are disclosed for scheduling volatile memory maintenance events. One embodiment is a method comprising: a memory controller determining a time-of-service (ToS) window for executing a maintenance event for a volatile memory device coupled to the memory controller via a memory data interface; the memory controller providing a signal to each of a plurality of processors on a system on chip (SoC) for scheduling the maintenance event; each of the plurality of processors independently generating in response to the signal a corresponding schedule notification for the maintenance event; and the memory controller determining when to execute the maintenance event in response to receiving one or more of the schedule notifications generated by the plurality of processors and based on a processor priority scheme.

    Abstract translation: 公开了用于调度易失性存储器维护事件的系统，方法和计算机程序。 一个实施例是一种方法，包括：存储器控制器，其确定用于经由存储器数据接口耦合到存储器控制器的易失性存储器设备执行维护事件的服务时间（ToS）窗口; 所述存储器控制器为片上系统（SoC）上的多个处理器中的每一个提供信号，用于调度所述维护事件; 所述多个处理器中的每一个独立地响应于所述信号产生用于所述维护事件的对应的调度通知; 并且所述存储器控制器响应于接收到由所述多个处理器产生的所述调度通知中的一个或多个并且基于处理器优先级方案来确定何时执行所述维护事件。

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