公开(公告)号：US20180342515A1

公开(公告)日：2018-11-29

申请号：US16057036

申请日：2018-08-07

Applicant: QUALCOMM Incorporated

Inventor： Seid Hadi RASOULI ,  Animesh DATTA ,  Ohsang KWON

IPC: H01L27/092 ,  H03K17/687 ,  H03K17/16 ,  H01L21/8238 ,  H01L23/535 ,  H01L27/02

CPC classification number: H01L27/0921 ,  H01L21/823871 ,  H01L23/4824 ,  H01L23/522 ,  H01L23/535 ,  H01L27/0207 ,  H01L27/092 ,  H01L2924/0002 ,  H03K17/168 ,  H03K17/6872 ,  H01L2924/00

Abstract: A first interconnect on an interconnect level connects a first subset of PMOS drains together of a CMOS device. A second interconnect on the interconnect level connects a second subset of the PMOS drains together. The second subset of the PMOS drains is different than the first subset of the PMOS drains. The first interconnect and the second interconnect are disconnected on the interconnect level. A third interconnect on the interconnect level connects a first subset of NMOS drains together of the CMOS device. A fourth interconnect on the interconnect level connects a second subset of the NMOS drains together. The second subset of the NMOS drains is different than the first subset of the NMOS drains. The third interconnect and the fourth interconnect are disconnected on the interconnect level. The first, second, third, and fourth interconnects are coupled together through at least one other interconnect level.

公开(公告)号：US20170257080A1

公开(公告)日：2017-09-07

申请号：US15061055

申请日：2016-03-04

Applicant: QUALCOMM Incorporated

Inventor： Seid Hadi RASOULI ,  Xiangdong CHEN ,  Venugopal BOYNAPALLI

IPC: H03K3/012 ,  H03K3/356

CPC classification number: H03K3/012 ,  H03K3/356104 ,  H03K3/35625

Abstract: In one example, the apparatus includes a first AND gate, a second AND gate, a first NOR gate, a second NOR gate, a third NOR gate, a first inverter, and a second inverter. The first AND gate output is coupled to the first NOR gate first input. The first NOR gate output is coupled to the second NOR gate first input. The second NOR gate output is coupled to the first NOR gate second input. The first inverter output is coupled to the first AND gate second input and the second NOR gate second input. The second AND gate first input is coupled to the first inverter output. The third NOR gate first input is coupled to the second NOR gate output. The third NOR gate second input is coupled to the second AND gate output. The second inverter output is coupled to the second AND gate second input.

公开(公告)号：US20180211957A1

公开(公告)日：2018-07-26

申请号：US15927539

申请日：2018-03-21

Applicant: QUALCOMM Incorporated

Inventor： Seid Hadi RASOULI ,  Michael BRUNOLLI ,  Christine HAU-RIEGE ,  Mickael Sebtastien Alain MALABRY ,  Sucheta Kumar HARISH ,  Prathiba BALASUBRAMANIAN ,  Kamesh MEDISETTI ,  Nikolay BOMSHTEIN ,  Animesh DATTA ,  Ohsang KWON

IPC: H01L27/092 ,  H01L27/02

CPC classification number: H01L27/0921 ,  H01L21/823871 ,  H01L23/4824 ,  H01L23/522 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/092 ,  H01L2924/0002 ,  H03K17/168 ,  H03K17/6872 ,  H01L2924/00

Abstract: A CMOS device with a plurality of PMOS transistors and a plurality of NMOS transistors includes a first interconnect and a second interconnect on an interconnect level connecting a first subset and a second subset of PMOS drains together, respectively. The first and second subsets are different and the first and second interconnect are disconnected on the interconnect level. A third interconnect and a fourth interconnect on the interconnect level connect a first subset and a second subset of the NMOS drains together, respectively. The third interconnect and the fourth interconnect are disconnected on the interconnect level. The first, second, third, fourth interconnects are coupled together through at least one other interconnect level. Additional interconnects on the interconnect level connect the first and third interconnects together, and the second and fourth interconnects together, to provide parallel current paths with a current path through the at least one other interconnect level.

公开(公告)号：US20180158506A1

公开(公告)日：2018-06-07

申请号：US15370892

申请日：2016-12-06

Applicant: QUALCOMM Incorporated

Inventor： Dorav KUMAR ,  Venkat NARAYANAN ,  Bilal ZAFAR ,  Seid Hadi RASOULI ,  Venugopal BOYNAPALLI

IPC: G11C11/4094 ,  G11C11/4076 ,  G06F1/12 ,  G06F1/06

CPC classification number: G11C11/4094 ,  G06F1/06 ,  G06F1/12 ,  G06F13/1689 ,  G11C7/222 ,  G11C11/4076

Abstract: The apparatus provided includes a memory. The memory is configured to receive a memory clock. The apparatus also includes a single stage logic gate configured to generate the memory clock from a reference clock. The memory clock is a gated clock. Additionally, the memory clock has a wider pulse width than the reference clock. In an example, the single stage logic gate comprises a pull-up circuit configured to pull-up the memory clock, and a pull-down circuit coupled to pull-down the memory clock. In an example, the pull-up and the pull-down circuits are configured to be controlled by the reference clock, a delayed reference clock, and a gating signal. An example further includes a delay circuit configured to generate the delayed reference clock from the reference clock. An example further includes a latch configured to generate the gating signal.

公开(公告)号：US20170373689A1

公开(公告)日：2017-12-28

申请号：US15192872

申请日：2016-06-24

Applicant: QUALCOMM Incorporated

Inventor： Dorav KUMAR ,  Venkatasubramanian NARAYANAN ,  Bala Krishna THALLA ,  Seid Hadi RASOULI ,  Radhika Vinayak GUTTAL ,  Sivakumar PATURI

IPC: H03K19/003 ,  H01L23/528 ,  H01L27/02 ,  H01L27/088

CPC classification number: H03K19/00361 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/088 ,  H03K19/17736 ,  H03K19/17744

Abstract: A MOS device may include a first logic component with a first input located on a second track and a first output located on the third track. The MOS device may include a second logic component with a second input located on the fourth track and a second output located on a fifth track. For example, the MOS device includes a first interconnect on a Mx layer that is coupled to the first input on the second track. In another example, the MOS device includes a second interconnect on the Mx layer that is coupled to the first output on the third track. The MOS device includes a third interconnect on a My layer that is coupled to the second input on the fourth track. Still further, the MOS device includes a fourth interconnect on the My layer that is coupled to the second output on the fifth track.

公开(公告)号：US20170221826A1

公开(公告)日：2017-08-03

申请号：US15493008

申请日：2017-04-20

Applicant: QUALCOMM Incorporated

Inventor： Seid Hadi RASOULI ,  Animesh DATTA ,  Ohsang KWON

IPC: H01L23/535 ,  H01L27/092 ,  H01L21/8238 ,  H01L27/02

CPC classification number: H01L27/0921 ,  H01L21/823871 ,  H01L23/4824 ,  H01L23/522 ,  H01L23/535 ,  H01L27/0207 ,  H01L27/092 ,  H01L2924/0002 ,  H03K17/168 ,  H03K17/6872 ,  H01L2924/00

Abstract: A first interconnect on an interconnect level connects a first subset of PMOS drains together of a CMOS device. A second interconnect on the interconnect level connects a second subset of the PMOS drains together. The second subset of the PMOS drains is different than the first subset of the PMOS drains. The first interconnect and the second interconnect are disconnected on the interconnect level. A third interconnect on the interconnect level connects a first subset of NMOS drains together of the CMOS device. A fourth interconnect on the interconnect level connects a second subset of the NMOS drains together. The second subset of the NMOS drains is different than the first subset of the NMOS drains. The third interconnect and the fourth interconnect are disconnected on the interconnect level. The first, second, third, and fourth interconnects are coupled together though at least one other interconnect level.

公开(公告)号：US20150054567A1

公开(公告)日：2015-02-26

申请号：US13975074

申请日：2013-08-23

Applicant: QUALCOMM Incorporated

Inventor： Seid Hadi RASOULI ,  Animesh DATTA ,  Ohsang KWON

IPC: H01L27/092 ,  H03K17/687 ,  H03K17/16 ,  H01L21/8238

CPC classification number: H01L27/0921 ,  H01L21/823871 ,  H01L23/4824 ,  H01L23/522 ,  H01L23/535 ,  H01L27/0207 ,  H01L27/092 ,  H01L2924/0002 ,  H03K17/168 ,  H03K17/6872 ,  H01L2924/00

Abstract: A first interconnect on an interconnect level connects a first subset of PMOS drains together of a CMOS device. A second interconnect on the interconnect level connects a second subset of the PMOS drains together. The second subset of the PMOS drains is different than the first subset of the PMOS drains. The first interconnect and the second interconnect are disconnected on the interconnect level. A third interconnect on the interconnect level connects a first subset of NMOS drains together of the CMOS device. A fourth interconnect on the interconnect level connects a second subset of the NMOS drains together. The second subset of the NMOS drains is different than the first subset of the NMOS drains. The third interconnect and the fourth interconnect are disconnected on the interconnect level. The first, second, third, and fourth interconnects are coupled together though at least one other interconnect level.

Abstract translation: 互连电平上的第一互连将CMOS器件的PMOS漏极的第一子集连接在一起。 互连层上的第二互连将PMOS排水沟的第二子集连接在一起。 PMOS漏极的第二子集不同于PMOS漏极的第一子集。 第一互连和第二互连在互连级别上断开连接。 互连电平上的第三互连将CMOS器件的NMOS漏极的第一子集连接在一起。 互连电平上的第四互连将NMOS漏极的第二子集连接在一起。 NMOS漏极的第二子集与NMOS漏极的第一子集不同。 第三互连和第四互连在互连级别上断开。 第一，第二，第三和第四互连通过至少一个其它互连级连接在一起。

公开(公告)号：US20200168604A1

公开(公告)日：2020-05-28

申请号：US16777639

申请日：2020-01-30

Applicant: QUALCOMM Incorporated

Inventor： Seid Hadi RASOULI ,  Michael Joseph BRUNOLLI ,  Christine Sung-An HAU-RIEGE ,  Mickael MALABRY ,  Sucheta Kumar HARISH ,  Prathiba BALASUBRAMANIAN ,  Kamesh MEDISETTI ,  Nikolay BOMSHTEIN ,  Animesh DATTA ,  Ohsang KWON

IPC: H01L27/092 ,  H03K17/687 ,  H03K17/16 ,  H01L21/8238 ,  H01L27/02 ,  H01L23/482 ,  H01L23/528

Abstract: A CMOS device with a plurality of PMOS transistors each having a PMOS drain and a plurality of NMOS transistors each having an NMOS drain includes a first interconnect and a second interconnect. The first interconnect is on an interconnect level extending in a length direction to connect the PMOS drains together, and the second interconnect is on the interconnect level extending in the length direction to connect the NMOS drains together. A set of interconnects on at least one additional interconnect level physically couple the first interconnect and the second interconnect to an output of the CMOS device. A third interconnect on the interconnect level extends perpendicular to the length direction and offset from the set of interconnects. The third interconnect is capable of flowing current from the PMOS drains or from the NMOS drains to the output of the CMOS device.

公开(公告)号：US20200152630A1

公开(公告)日：2020-05-14

申请号：US16744227

申请日：2020-01-16

Applicant: QUALCOMM Incorporated

Inventor： Seid Hadi RASOULI ,  Animesh DATTA ,  Ohsang KWON

IPC: H01L27/092 ,  H01L23/535 ,  H03K17/687 ,  H03K17/16 ,  H01L21/8238 ,  H01L27/02 ,  H01L23/482

Abstract: A first interconnect on an interconnect level connects a first subset of PMOS drains together of a CMOS device. A second interconnect on the interconnect level connects a second subset of the PMOS drains together. The second subset of the PMOS drains is different than the first subset of the PMOS drains. The first interconnect and the second interconnect are disconnected on the interconnect level. A third interconnect on the interconnect level connects a first subset of NMOS drains together of the CMOS device. A fourth interconnect on the interconnect level connects a second subset of the NMOS drains together. The second subset of the NMOS drains is different than the first subset of the NMOS drains. The third interconnect and the fourth interconnect are disconnected on the interconnect level. The first, second, third, and fourth interconnects are coupled together through at least one other interconnect level.

公开(公告)号：US20160211846A1

公开(公告)日：2016-07-21

申请号：US14598182

申请日：2015-01-15

Applicant: QUALCOMM INCORPORATED

Inventor： Seid Hadi RASOULI ,  Steven James DILLEN ,  Animesh DATTA

IPC: H03K19/00 ,  H03K17/687

CPC classification number: H03K19/0016 ,  H03K17/6872

Abstract: A CGC includes an enable module and a latch module. The enable module has an enable module input and an enable module output. The latch module has latch module inputs and a latch module output. The latch module inputs include a latch module clock input for receiving a clock and a latch module enable input for receiving the enable module output. The latch module enable input is coupled to the enable module output. The latch module is configured to enable and to disable the clock via the latch module output based on the enable module input. The latch module includes an internal enable node that is the latch module output. The latch module is configured to cause the internal enable node to transition from low to high as a function of the enable module output and ĒC, where E is the internal enable node and C is the clock.

Abstract translation: CGC包括使能模块和锁存模块。 启用模块具有使能模块输入和使能模块输出。 锁存模块具有锁存模块输入和锁存模块输出。 锁存模块输入包括用于接收时钟的锁存模块时钟输入和用于接收使能模块输出的锁存模块使能输入。 锁存模块使能输入耦合到使能模块输出。 锁存模块被配置为通过基于使能模块输入的锁存模块输出来启用和禁用时钟。 锁存模块包括作为锁存模块输出的内部使能节点。 锁存模块被配置为使内部使能节点根据使能模块输出和ĒC的功能从低电平转换到高电平，其中E是内部使能节点，C是时钟。