公开(公告)号：US20170373689A1

公开(公告)日：2017-12-28

申请号：US15192872

申请日：2016-06-24

Applicant: QUALCOMM Incorporated

Inventor： Dorav KUMAR ,  Venkatasubramanian NARAYANAN ,  Bala Krishna THALLA ,  Seid Hadi RASOULI ,  Radhika Vinayak GUTTAL ,  Sivakumar PATURI

IPC: H03K19/003 ,  H01L23/528 ,  H01L27/02 ,  H01L27/088

CPC classification number: H03K19/00361 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/088 ,  H03K19/17736 ,  H03K19/17744

Abstract: A MOS device may include a first logic component with a first input located on a second track and a first output located on the third track. The MOS device may include a second logic component with a second input located on the fourth track and a second output located on a fifth track. For example, the MOS device includes a first interconnect on a Mx layer that is coupled to the first input on the second track. In another example, the MOS device includes a second interconnect on the Mx layer that is coupled to the first output on the third track. The MOS device includes a third interconnect on a My layer that is coupled to the second input on the fourth track. Still further, the MOS device includes a fourth interconnect on the My layer that is coupled to the second output on the fifth track.