公开(公告)号：US20180211957A1

公开(公告)日：2018-07-26

申请号：US15927539

申请日：2018-03-21

Applicant: QUALCOMM Incorporated

Inventor： Seid Hadi RASOULI ,  Michael BRUNOLLI ,  Christine HAU-RIEGE ,  Mickael Sebtastien Alain MALABRY ,  Sucheta Kumar HARISH ,  Prathiba BALASUBRAMANIAN ,  Kamesh MEDISETTI ,  Nikolay BOMSHTEIN ,  Animesh DATTA ,  Ohsang KWON

IPC: H01L27/092 ,  H01L27/02

CPC classification number: H01L27/0921 ,  H01L21/823871 ,  H01L23/4824 ,  H01L23/522 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/092 ,  H01L2924/0002 ,  H03K17/168 ,  H03K17/6872 ,  H01L2924/00

Abstract: A CMOS device with a plurality of PMOS transistors and a plurality of NMOS transistors includes a first interconnect and a second interconnect on an interconnect level connecting a first subset and a second subset of PMOS drains together, respectively. The first and second subsets are different and the first and second interconnect are disconnected on the interconnect level. A third interconnect and a fourth interconnect on the interconnect level connect a first subset and a second subset of the NMOS drains together, respectively. The third interconnect and the fourth interconnect are disconnected on the interconnect level. The first, second, third, fourth interconnects are coupled together through at least one other interconnect level. Additional interconnects on the interconnect level connect the first and third interconnects together, and the second and fourth interconnects together, to provide parallel current paths with a current path through the at least one other interconnect level.

公开(公告)号：US20180129267A1

公开(公告)日：2018-05-10

申请号：US15863155

申请日：2018-01-05

Applicant: QUALCOMM Incorporated

Inventor： Michael BRUNOLLI ,  Stephen THILENIUS ,  Patrick ISAKANIAN ,  Vaishnav Srinivas

IPC: G06F1/32 ,  H04L25/02 ,  G11C11/4074 ,  G11C7/10 ,  G06F13/42 ,  G06F13/40 ,  G06F13/16

CPC classification number: G06F1/3275 ,  G06F1/32 ,  G06F1/3209 ,  G06F1/3287 ,  G06F1/3296 ,  G06F13/16 ,  G06F13/4086 ,  G06F13/4243 ,  G11C7/1072 ,  G11C11/4074 ,  H04L25/0264 ,  H04L25/0278 ,  Y02D10/14 ,  Y02D10/172 ,  Y02D50/20

Abstract: A memory interface includes: a pull-up device and a pull-down device, wherein the pull-up device couples between a power rail and a data line, and wherein the pull-down device couples between the data line and ground; and a power supply configured to supply a first power supply voltage to the power rail during a terminated data transmission mode in which a receiving memory interface coupled to the data line has an active on-die termination, and wherein the power supply is further configured to supply a second power supply voltage to the power rail during an unterminated data transmission mode in which the on-die termination does not load the data line, the second power supply voltage being less than the first power supply voltage.