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公开(公告)号:US20200051604A1
公开(公告)日:2020-02-13
申请号:US16655034
申请日:2019-10-16
Applicant: QUALCOMM Incorporated
Inventor: Masoud ZAMANI , Bilal ZAFAR , Venkatasubramanian NARAYANAN
Abstract: A memory circuit according to some examples may include a clock delay circuit that use a polarity of a write enable signal to determine an operation (i.e. write or read) on the memory that provides the desired clock latency to the memory. The clock delay circuit may have a low skew portion and a high skew portion. The selection of the high skew portion or low skew portion may depend on the status of the write enable line, such as a polarity or logical value.
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公开(公告)号:US20190115058A1
公开(公告)日:2019-04-18
申请号:US16206998
申请日:2018-11-30
Applicant: QUALCOMM Incorporated
Inventor: Masoud ZAMANI , Bilal ZAFAR , Venkatasubramanian NARAYANAN
Abstract: A memory circuit according to some examples may include a clock delay circuit that use a polarity of a write enable signal to determine an operation (i.e. write or read) on the memory that provides the desired clock latency to the memory. The clock delay circuit may have a low skew portion and a high skew portion. The selection of the high skew portion or low skew portion may depend on the status of the write enable line, such as a polarity or logical value.
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公开(公告)号:US20180158506A1
公开(公告)日:2018-06-07
申请号:US15370892
申请日:2016-12-06
Applicant: QUALCOMM Incorporated
Inventor: Dorav KUMAR , Venkat NARAYANAN , Bilal ZAFAR , Seid Hadi RASOULI , Venugopal BOYNAPALLI
IPC: G11C11/4094 , G11C11/4076 , G06F1/12 , G06F1/06
CPC classification number: G11C11/4094 , G06F1/06 , G06F1/12 , G06F13/1689 , G11C7/222 , G11C11/4076
Abstract: The apparatus provided includes a memory. The memory is configured to receive a memory clock. The apparatus also includes a single stage logic gate configured to generate the memory clock from a reference clock. The memory clock is a gated clock. Additionally, the memory clock has a wider pulse width than the reference clock. In an example, the single stage logic gate comprises a pull-up circuit configured to pull-up the memory clock, and a pull-down circuit coupled to pull-down the memory clock. In an example, the pull-up and the pull-down circuits are configured to be controlled by the reference clock, a delayed reference clock, and a gating signal. An example further includes a delay circuit configured to generate the delayed reference clock from the reference clock. An example further includes a latch configured to generate the gating signal.
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公开(公告)号:US20180082724A1
公开(公告)日:2018-03-22
申请号:US15273606
申请日:2016-09-22
Applicant: QUALCOMM Incorporated
Inventor: Masoud ZAMANI , Bilal ZAFAR , Venkatasubramanian NARAYANAN
CPC classification number: G11C7/222 , H03K5/133 , H03K19/20 , H03K2005/00019
Abstract: A memory circuit according to some examples may include a clock delay circuit that use a polarity of a write enable signal to determine an operation (i.e. write or read) on the memory that provides the desired clock latency to the memory. The clock delay circuit may have a low skew portion and a high skew portion. The selection of the high skew portion or low skew portion may depend on the status of the write enable line, such as a polarity or logical value.
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