APPARATUS AND METHOD OF CLOCK SHAPING FOR MEMORY

    公开(公告)号:US20200051604A1

    公开(公告)日:2020-02-13

    申请号:US16655034

    申请日:2019-10-16

    Abstract: A memory circuit according to some examples may include a clock delay circuit that use a polarity of a write enable signal to determine an operation (i.e. write or read) on the memory that provides the desired clock latency to the memory. The clock delay circuit may have a low skew portion and a high skew portion. The selection of the high skew portion or low skew portion may depend on the status of the write enable line, such as a polarity or logical value.

    APPARATUS AND METHOD OF CLOCK SHAPING FOR MEMORY

    公开(公告)号:US20190115058A1

    公开(公告)日:2019-04-18

    申请号:US16206998

    申请日:2018-11-30

    Abstract: A memory circuit according to some examples may include a clock delay circuit that use a polarity of a write enable signal to determine an operation (i.e. write or read) on the memory that provides the desired clock latency to the memory. The clock delay circuit may have a low skew portion and a high skew portion. The selection of the high skew portion or low skew portion may depend on the status of the write enable line, such as a polarity or logical value.

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