公开(公告)号：US20200051604A1

公开(公告)日：2020-02-13

申请号：US16655034

申请日：2019-10-16

Applicant: QUALCOMM Incorporated

Inventor： Masoud ZAMANI ,  Bilal ZAFAR ,  Venkatasubramanian NARAYANAN

IPC: G11C7/22 ,  H03K5/133 ,  H03K19/20

Abstract: A memory circuit according to some examples may include a clock delay circuit that use a polarity of a write enable signal to determine an operation (i.e. write or read) on the memory that provides the desired clock latency to the memory. The clock delay circuit may have a low skew portion and a high skew portion. The selection of the high skew portion or low skew portion may depend on the status of the write enable line, such as a polarity or logical value.

公开(公告)号：US20180082724A1

公开(公告)日：2018-03-22

申请号：US15273606

申请日：2016-09-22

Applicant: QUALCOMM Incorporated

Inventor： Masoud ZAMANI ,  Bilal ZAFAR ,  Venkatasubramanian NARAYANAN

IPC: G11C7/22 ,  H03K5/13 ,  H03K19/20

CPC classification number: G11C7/222 ,  H03K5/133 ,  H03K19/20 ,  H03K2005/00019

Abstract: A memory circuit according to some examples may include a clock delay circuit that use a polarity of a write enable signal to determine an operation (i.e. write or read) on the memory that provides the desired clock latency to the memory. The clock delay circuit may have a low skew portion and a high skew portion. The selection of the high skew portion or low skew portion may depend on the status of the write enable line, such as a polarity or logical value.

公开(公告)号：US20230396253A1

公开(公告)日：2023-12-07

申请号：US17805014

申请日：2022-06-01

Applicant: QUALCOMM Incorporated

Inventor： Kevin BOWLES ,  Chirag MAHESHWARI ,  Divya GANGADHARAN ,  Venkat NARAYANAN ,  Masoud ZAMANI

IPC: H03K19/17736 ,  H03K19/003 ,  H03K19/20

CPC classification number: H03K19/1774 ,  H03K19/17744 ,  H03K19/00323 ,  H03K19/20

Abstract: In certain aspects, an apparatus includes a first gating circuit having an input and an output, wherein the input of the first gating circuit is configured to receive a first clock signal. The apparatus also includes a delay circuit having an input and an output, wherein the input of the delay circuit is coupled to the output of the first gating circuit. The apparatus further includes a control circuit configured to receive an enable signal, detect a logic state at the output of the delay circuit, and cause the first gating circuit to pass or gate the first clock signal based on the enable signal and the detected logic state at the output of the delay circuit.

公开(公告)号：US20190115058A1

公开(公告)日：2019-04-18

申请号：US16206998

申请日：2018-11-30

Applicant: QUALCOMM Incorporated

Inventor： Masoud ZAMANI ,  Bilal ZAFAR ,  Venkatasubramanian NARAYANAN

IPC: G11C7/22 ,  H03K19/20 ,  H03K5/133

Abstract: A memory circuit according to some examples may include a clock delay circuit that use a polarity of a write enable signal to determine an operation (i.e. write or read) on the memory that provides the desired clock latency to the memory. The clock delay circuit may have a low skew portion and a high skew portion. The selection of the high skew portion or low skew portion may depend on the status of the write enable line, such as a polarity or logical value.