公开(公告)号：US20230197554A1

公开(公告)日：2023-06-22

申请号：US17558508

申请日：2021-12-21

Applicant: QUALCOMM Incorporated

Inventor： Je-Hsiung LAN ,  Jonghae KIM ,  Ranadeep DUTTA

IPC: H01L23/367 ,  H01L25/065 ,  H01L21/48 ,  H01L25/00

CPC classification number: H01L23/3677 ,  H01L25/0655 ,  H01L21/4871 ,  H01L25/50

Abstract: Disclosed are apparatuses and techniques for fabricating an apparatus including a semiconductor device. The semiconductor device may include: a die, a thermally conductive interface that includes a thermal bridge interposer (THBI) structure, and a substrate. The die is coupled to the substrate by the thermally conductive interface and at least a portion of the die is coupled to the substrate by the THBI structure.

公开(公告)号：US20250037923A1

公开(公告)日：2025-01-30

申请号：US18360570

申请日：2023-07-27

Applicant: QUALCOMM Incorporated

Inventor： Kai LIU ,  Jui-Yi CHIU ,  Jonghae KIM ,  Nosun PARK ,  Je-Hsiung LAN

IPC: H01F27/28 ,  H01F41/04 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  H01L25/18 ,  H01L27/01

Abstract: A package comprising an integrated device and a substrate coupled to the integrated device through a plurality of solder interconnects. The substrate comprises at least one magnetic layer, at least one dielectric layer; and a plurality of interconnects. The plurality of interconnects comprise a first set of interconnects that are configured to operate as a first inductor and a second set of interconnects that are configured to operate as a second inductor. The second inductor and the first inductor are configured to operate as inductively coupled inductors.

公开(公告)号：US20240322417A1

公开(公告)日：2024-09-26

申请号：US18189684

申请日：2023-03-24

Applicant: QUALCOMM Incorporated

Inventor： Kai LIU ,  Jonghae KIM ,  Jui-Yi CHIU ,  Nosun PARK ,  Je-Hsiung LAN

IPC: H01P7/10 ,  H01P11/00 ,  H03B5/12

CPC classification number: H01P7/10 ,  H01P11/008 ,  H03B5/1206

Abstract: In an aspect, an apparatus is disclosed that includes a surface-mounted integrated circuit package housing an active oscillator circuit; an integrated ceramic resonator formed from a ceramic substrate having an upper planar surface receiving the surface-mounted integrated circuit package, the integrated ceramic resonator including a plurality of conductive walls forming a conductive periphery of a ceramic cavity in the ceramic substrate, a conductive rod extending vertically into the ceramic cavity, wherein the conductive rod is isolated from contact with the conductive periphery of the ceramic cavity, a first conductive material extending vertically through the upper planar surface of the ceramic substrate for connecting the conductive periphery of the ceramic cavity to the surface-mounted integrated circuit package housing the active oscillator circuit; and a second conductive material extending through the upper planar surface of the ceramic substrate for connecting the conductive rod to the surface-mounted integrated circuit package.

公开(公告)号：US20240105760A1

公开(公告)日：2024-03-28

申请号：US17951839

申请日：2022-09-23

Applicant: QUALCOMM Incorporated

Inventor： Je-Hsiung LAN ,  Jonghae KIM ,  Jui-Yi CHIU ,  Kai LIU ,  Nosun PARK

IPC: H01L49/02 ,  H01F27/24 ,  H01F27/28 ,  H01F41/04 ,  H01L25/16 ,  H01L25/18 ,  H01L27/01

CPC classification number: H01L28/10 ,  H01F27/24 ,  H01F27/2804 ,  H01F41/042 ,  H01F41/043 ,  H01L25/16 ,  H01L25/18 ,  H01L27/01

Abstract: A device is described. The device includes a substrate having a first cavity. The device also includes a first redistribution layer (RDL) on sidewalls and a base of the first cavity in the substrate and on a first surface of the substrate. The device further includes a fill material in the first cavity.

公开(公告)号：US20240096817A1

公开(公告)日：2024-03-21

申请号：US17932788

申请日：2022-09-16

Applicant: QUALCOMM Incorporated

Inventor： Ranadeep DUTTA ,  Jonghae KIM ,  Je-Hsiung LAN

IPC: H01L23/552 ,  H01L21/48 ,  H01L23/00 ,  H01L23/373 ,  H01L23/498 ,  H01L23/528 ,  H01L23/66 ,  H01Q1/02 ,  H01Q1/22 ,  H01Q3/36 ,  H01Q9/04 ,  H01Q21/06

CPC classification number: H01L23/552 ,  H01L21/4853 ,  H01L23/3736 ,  H01L23/49838 ,  H01L23/5283 ,  H01L23/5286 ,  H01L23/66 ,  H01L24/08 ,  H01Q1/02 ,  H01Q1/2283 ,  H01Q3/36 ,  H01Q9/0414 ,  H01Q21/065 ,  H01L23/49816 ,  H01L2223/6616 ,  H01L2223/6644 ,  H01L2223/6677 ,  H01L2224/08225 ,  H01L2924/14215 ,  H01L2924/3025 ,  H01L2924/351

Abstract: Disclosed are techniques for on-chip electromagnetic interference (EMI) shielding. In an aspect, an integrated circuit includes a noise-sensitive device, a first metallization layer disposed on a first side of the noise-sensitive device, wherein the first metallization layer includes a plurality of conductive routing layers, and wherein conductive routing within the plurality of conductive routing layers is configured as a first side of an on-chip electromagnetic interference (EMI) shield around the first side of the noise-sensitive device, and a second metallization layer disposed on a second side of the noise-sensitive device opposite the first side of the noise-sensitive device, wherein the second metallization layer includes one or more conductive routing layers, and wherein conductive routing within the one or more conductive routing layers is configured as a second side of the on-chip EMI shield around the second side of the noise-sensitive device.

公开(公告)号：US20230307355A1

公开(公告)日：2023-09-28

申请号：US17705041

申请日：2022-03-25

Applicant: QUALCOMM Incorporated

Inventor： Kai LIU ,  Je-Hsiung LAN ,  Jonghae KIM

IPC: H01L23/522 ,  H01L49/02

CPC classification number: H01L23/5227 ,  H01L23/5226 ,  H01L23/5222 ,  H01L28/10 ,  H01L24/13

Abstract: An integrated device that includes a die substrate comprising a plurality of transistors, an interconnection portion coupled to the die substrate, and a packaging portion coupled to the interconnection portion. The interconnection portion includes at least one die dielectric layer and a plurality of die interconnects coupled to the plurality of transistors. The packaging portion includes at least one magnetic layer and a plurality of metallization interconnects coupled to the plurality of die interconnects.

公开(公告)号：US20220302107A1

公开(公告)日：2022-09-22

申请号：US17206950

申请日：2021-03-19

Applicant: QUALCOMM Incorporated

Inventor： Ranadeep DUTTA ,  Jonghae KIM ,  Je-Hsiung LAN

IPC: H01L27/06 ,  H01L49/02 ,  H01L29/20 ,  H01L29/16 ,  H01L29/04 ,  H01L29/778 ,  H01L23/66 ,  H01L29/66 ,  H01L21/8258

Abstract: A radio frequency integrated circuit (RFIC) includes a bulk semiconductor substrate. The RFIC also includes a compound semiconductor field effect transistor (FET). The compound semiconductor FET is composed of a gallium nitride (GaN) epitaxial stack in a trench in the bulk semiconductor substrate having sidewall spacers. The sidewall spacers are between the GaN epitaxial stack and sidewalls of the trench. A carbonized surface layer is at a base of the trench and coupled to the GaN epitaxial stack. The RFIC further includes a complementary metal oxide semiconductor (CMOS) transistor integrated with the compound semiconductor FET on the bulk semiconductor substrate.

公开(公告)号：US20210391234A1

公开(公告)日：2021-12-16

申请号：US16898096

申请日：2020-06-10

Applicant: QUALCOMM Incorporated

Inventor： Je-Hsiung LAN ,  Jonghae KIM ,  Ranadeep DUTTA

IPC: H01L23/367 ,  H01L23/373 ,  H01L21/48

Abstract: A semiconductor package is described. The semiconductor package includes a passive substrate and a first integrated passive device (IPD) in a first interlayer-dielectric (ILD) layer on the passive substrate. The semiconductor package also includes a second ILD layer on the first ILD layer. The semiconductor package further includes a second IPD in a third ILD layer on the second ILD layer. The semiconductor package also includes a thermal mitigation structure on inductive elements of the second IPD.

公开(公告)号：US20200381398A1

公开(公告)日：2020-12-03

申请号：US16600300

申请日：2019-10-11

Applicant: QUALCOMM Incorporated

Inventor： Je-Hsiung LAN ,  Jonghae KIM ,  Ranadeep DUTTA

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L23/48 ,  H01L25/00

Abstract: 3D integrated circuit (3DIC) device architecture is disclosed for monolithically heterogeneous integration of III-V devices over Si-CMOS devices with high-quality (HQ) integrated passives devices (IPD) or re-distributed layers (RDL). In addition, a thermal spreader may be added over the upper III-V tier to enhance device power performance (e.g., PAE for PA) and device reliability (e.g., with a reduced Tj/junction temperature).

公开(公告)号：US20200350425A1

公开(公告)日：2020-11-05

申请号：US16401240

申请日：2019-05-02

Applicant: QUALCOMM Incorporated

Inventor： Ranadeep DUTTA ,  Jonghae KIM ,  Je-Hsiung LAN

IPC: H01L29/778 ,  H01L29/66 ,  H01L27/088 ,  H01L29/16 ,  H01L29/20

Abstract: A semiconductor device having heterogeneous transistors integrated on a diamond substrate. An example semiconductor device generally includes a diamond substrate, a first transistor disposed above the diamond substrate, the first transistor comprising gallium nitride, and a second transistor disposed above the diamond substrate, the second transistor comprising a different semiconductor than the first transistor.