公开(公告)号：US20150248741A1

公开(公告)日：2015-09-03

申请号：US14194743

申请日：2014-03-02

Applicant: QUALCOMM INCORPORATED

Inventor： ALI IRANLI ,  MOINUL H. KHAN ,  HAW-JING LO

IPC: G06T1/60

CPC classification number: G06T1/60 ,  G06F1/3218 ,  G06F1/3265 ,  G06F1/3275 ,  G09G2330/022 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/153 ,  Y02D50/20

Abstract: Systems, methods, and computer programs are disclosed for reducing power consumption for static image display refresh in a dynamic random access memory (DRAM) memory system. One such method comprises: prefetching static image frame content from a DRAM memory device into a system cache; during a static display refresh operation, a display processor reads the static image frame content from the system cache while the DRAM memory device is in a power-saving, self-refresh state; and the display processor feeding the static image frame content to a mobile display.

Abstract translation: 公开了用于降低动态随机存取存储器（DRAM）存储器系统中静态图像显示刷新的功耗的系统，方法和计算机程序。 一种这样的方法包括：将静态图像帧内容从DRAM存储器设备预取到系统高速缓存中; 在静态显示刷新操作期间，显示处理器在DRAM存储器件处于省电自刷新状态的同时从系统高速缓存读取静态图像帧内容; 并且显示处理器将静态图像帧内容馈送到移动显示器。

公开(公告)号：US20150121111A1

公开(公告)日：2015-04-30

申请号：US14062866

申请日：2013-10-24

Applicant: Qualcomm Incorporated

Inventor： DEXTER CHUN ,  HAW-JING LO

IPC: G06F1/32 ,  H03M13/23 ,  G11C11/4074

CPC classification number: G06F1/3275 ,  G11C11/4074 ,  H03M7/3079 ,  H03M7/40 ,  H03M13/235

Abstract: Systems and methods are disclosed for providing multi-user power saving codebook optimization. One such method comprises: generating a unique codebook for a plurality of computing devices, each unique codebook configured for encoding memory data in the corresponding computing device; providing the unique codebooks to the corresponding computing devices via a communications networks; receiving compression statistics from one or more of the computing devices via the communications network, the compression statistics related to the corresponding unique codebook; and generating an optimized codebook for at least one of the computing devices based on the received compression statistics.

Abstract translation: 公开了用于提供多用户功率节省码本优化的系统和方法。 一种这样的方法包括：为多个计算设备生成唯一的码本，每个唯一的码本被配置用于对相应的计算设备中的存储器数据进行编码; 通过通信网络向相应的计算设备提供唯一的码本; 经由通信网络从一个或多个计算设备接收压缩统计信息，与相应的唯一码本相关的压缩统计; 以及基于所接收的压缩统计信息为所述计算设备中的至少一个生成优化的码本。

公开(公告)号：US20160148670A1

公开(公告)日：2016-05-26

申请号：US14616720

申请日：2015-02-08

Applicant: QUALCOMM INCORPORATED

Inventor： NHON TOAI QUACH ,  VIRAT DEEPAK ,  OSCAR CABRAL ARIAS ,  YANRU LI ,  HAW-JING LO ,  MICHAEL DROP ,  VENKATA NARAYANA RAMESH PINNAMARAJU DURGA ,  MOINUL KHAN

IPC: G11C11/4074 ,  G06F1/32 ,  G11C11/409

CPC classification number: G06F1/3275 ,  G06F1/3287 ,  G06F2212/1028 ,  G06F2212/401 ,  G11C11/4074 ,  G11C11/409 ,  H03M7/30 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/171

Abstract: Various embodiments of systems and methods are disclosed for reducing volatile memory standby power in a portable computing device. One such method involves receiving a request for a volatile memory device to enter a standby power mode. One or more compression parameters are determined for compressing content stored in a plurality of banks of the volatile memory device. The stored content is compressed based on the one or more compression parameters to free-up at least one of the plurality of banks. The method disables self-refresh of at least a portion of one or more of the plurality of banks freed-up by the compression during the standby power mode.

Abstract translation: 公开了用于减少便携式计算设备中的易失性存储器待机功率的系统和方法的各种实施例。 一种这样的方法包括接收对易失性存储器设备进入待机功率模式的请求。 确定一个或多个压缩参数以压缩存储在易失性存储器件的多个组中的内容。 存储的内容基于一个或多个压缩参数被压缩以释放多个存储体中的至少一个存储体。 该方法禁用在待机功率模式期间由压缩释放的多个组中的一个或多个的至少一部分的自刷新。

公开(公告)号：US20150199134A1

公开(公告)日：2015-07-16

申请号：US14172173

申请日：2014-02-04

Applicant: QUALCOMM INCORPORATED

Inventor： MRIGANKA MONDAL ,  HAW-JING LO

IPC: G06F3/06 ,  G06F12/06 ,  G11C7/10

CPC classification number: G06F3/0611 ,  G06F3/0655 ,  G06F3/0673 ,  G06F12/0607 ,  G06F13/1626 ,  G06F2212/652 ,  G11C7/1042 ,  G11C7/1072 ,  G11C7/1075 ,  G11C11/4096 ,  Y02D10/14

Abstract: Systems, methods, and computer programs are disclosed for managing access requests to a DRAM memory device. One embodiment includes receiving memory access pattern data for at least one of a plurality of memory clients prior to a corresponding memory transaction with a DRAM memory device. Next, it is determined, based on the received memory access pattern data, that a future transaction of a first of the plurality of memory clients may create a future page conflict with a current transaction of a second of the plurality of memory clients. The future page conflict is then resolved by interleaving access to an associated bank in the DRAM memory device by the first and second memory clients according to the received memory access pattern data.

Abstract translation: 公开了用于管理对DRAM存储器件的访问请求的系统，方法和计算机程序。 一个实施例包括在与DRAM存储器设备进行相应的存储器交易之前接收多个存储器客户端中的至少一个的存储器访问模式数据。 接下来，基于接收到的存储器访问模式数据确定多个存储器客户端中的第一个的未来事务可以与多个存储器客户端中的第二个存储器客户端的当前事务产生未来页面冲突。 然后通过根据接收到的存储器访问模式数据，通过第一和第二存储器客户端交错对DRAM存储器设备中的相关联存储体的访问来解决未来页冲突。

公开(公告)号：US20150134989A1

公开(公告)日：2015-05-14

申请号：US14079620

申请日：2013-11-13

Applicant: Qualcomm Incorporated

Inventor： DEXTER CHUN ,  HAW-JING LO

IPC: G06F1/32

CPC classification number: G06F1/3275 ,  G06F1/32 ,  G06F1/3253 ,  G06F7/764 ,  G11C7/1006 ,  G11C7/1009 ,  G11C7/1057 ,  G11C7/1084 ,  G11C11/4096

Abstract: Systems and methods are disclosed for reducing memory I/O power. One embodiment is a system comprising a system on chip (SoC), a DRAM memory device, and a data masking power reduction module. The SoC comprises a memory controller. The DRAM memory device is coupled to the memory controller via a plurality of DQ pins. The data masking power reduction module comprises logic configured to drive the DQ pins to a power saving state during a data masking operation.

Abstract translation: 公开了用于降低存储器I / O功率的系统和方法。 一个实施例是包括片上系统（SoC），DRAM存储器件和数据屏蔽功率降低模块的系统。 SoC包括一个内存控制器。 DRAM存储器件通过多个DQ引脚耦合到存储器控制器。 数据屏蔽功率降低模块包括被配置为在数据屏蔽操作期间将DQ引脚驱动到功率节省状态的逻辑。

公开(公告)号：US20150121096A1

公开(公告)日：2015-04-30

申请号：US14062859

申请日：2013-10-24

Applicant: Qualcomm Incorporated

Inventor： DEXTER CHUN ,  HAW-JING LO

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0644 ,  G06F3/0673 ,  H03M7/40 ,  H03M7/6047

Abstract: Systems and methods are disclosed for conserving power consumption in a memory system. One such system comprises a system on chip (SoC) and an encoder. The SoC comprises one or more memory clients for accessing a dynamic random access memory (DRAM) memory system coupled to the SoC. The encoder resides on the SoC and is configured to reduce a data activity factor of memory data received from the memory clients by encoding the received memory data according to a compression scheme and providing the encoded memory data to the DRAM memory system. The DRAM memory system is configured to decode the encoded memory data according to the compression scheme into the received memory data.

Abstract translation: 公开了用于节省存储器系统中的功耗的系统和方法。 一种这样的系统包括片上系统（SoC）和编码器。 SoC包括用于访问耦合到SoC的动态随机存取存储器（DRAM）存储器系统的一个或多个存储器客户端。 编码器驻留在SoC上，并且被配置为通过根据压缩方案对接收的存储器数据进行编码来减少从存储器客户机接收的存储器数据的数据活动因子，并将编码的存储器数据提供给DRAM存储器系统。 DRAM存储器系统被配置为根据压缩方案将经编码的存储器数据解码为接收的存储器数据。

公开(公告)号：US20150089112A1

公开(公告)日：2015-03-26

申请号：US14033233

申请日：2013-09-20

Applicant: Qualcomm Incorporated

Inventor： HAW-JING LO ,  DEXTER CHUN

IPC: G06F13/40 ,  G06F1/32 ,  G06F13/16

CPC classification number: G06F13/4018 ,  G06F1/3253 ,  G06F1/3275 ,  G06F13/1678 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: Systems and methods are disclosed for conserving power consumption in a memory system. One such system comprises a DRAM memory system and a system on chip (SoC). The SoC is coupled to the DRAM memory system via a memory bus. The SoC comprises one or more memory controllers for processing memory requests from one or more memory clients for accessing the DRAM memory system. The one or more memory controllers are configured to selectively conserve memory power consumption by dynamically resizing a bus width of the memory bus.

Abstract translation: 公开了用于节省存储器系统中的功耗的系统和方法。 一种这样的系统包括DRAM存储器系统和片上系统（SoC）。 SoC通过存储器总线耦合到DRAM存储器系统。 SoC包括用于处理来自一个或多个存储器客户端的访问DRAM存储器系统的存储器请求的一个或多个存储器控制器。 一个或多个存储器控制器被配置为通过动态地调整存储器总线的总线宽度来选择性地节省存储器功耗。