公开(公告)号：US20140061642A1

公开(公告)日：2014-03-06

申请号：US13802759

申请日：2013-03-14

Applicant: QUALCOMM INCORPORATED

Inventor： Vaishnav Srinivas ,  Bernie Jord Yang ,  Michael Brunolli ,  David Ian West ,  Charles David Paynter

IPC: H01L23/00

CPC classification number: H01L24/17 ,  H01L21/563 ,  H01L22/32 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/02377 ,  H01L2224/0401 ,  H01L2224/05558 ,  H01L2224/0556 ,  H01L2224/05569 ,  H01L2224/11462 ,  H01L2224/13028 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13116 ,  H01L2224/13147 ,  H01L2224/14165 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/27462 ,  H01L2224/29028 ,  H01L2224/29078 ,  H01L2224/29147 ,  H01L2224/3012 ,  H01L2224/3213 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/831 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/07802 ,  H01L2924/381 ,  H01L2924/0105 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552

Abstract: Various aspects of an approach for routing die signals in an interior portion of a die using external interconnects are described herein. The approach provides for contacts coupled to circuits in the interior portion of the die, where the contacts are exposed to an exterior portion of the die. The external interconnects are configured to couple these contacts so that signals from the circuits in the interior portion of the die may be routed externally to the die. In various aspects of the disclosed approach, the external interconnects are protected by a packaging for the die.

Abstract translation: 这里描述了使用外部互连在芯片的内部部分中布线管芯信号的方法的各个方面。 该方法提供了耦合到管芯内部的电路的触点，其中触点暴露于管芯的外部部分。 外部互连被配置为耦合这些触点，使得来自芯片内部部分的电路的信号可以被外部引导到管芯。 在所公开的方法的各个方面，外部互连由模具的包装保护。

公开(公告)号：US09871012B2

公开(公告)日：2018-01-16

申请号：US13802759

申请日：2013-03-14

Applicant: QUALCOMM Incorporated

Inventor： Vaishnav Srinivas ,  Bernie Jord Yang ,  Michael Brunolli ,  David Ian West ,  Charles David Paynter

IPC: H01L23/00 ,  H01L21/66 ,  H01L21/56

CPC classification number: H01L24/17 ,  H01L21/563 ,  H01L22/32 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/02377 ,  H01L2224/0401 ,  H01L2224/05558 ,  H01L2224/0556 ,  H01L2224/05569 ,  H01L2224/11462 ,  H01L2224/13028 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13116 ,  H01L2224/13147 ,  H01L2224/14165 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/27462 ,  H01L2224/29028 ,  H01L2224/29078 ,  H01L2224/29147 ,  H01L2224/3012 ,  H01L2224/3213 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/831 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/07802 ,  H01L2924/381 ,  H01L2924/0105 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552

Abstract: Various aspects of an approach for routing die signals in an interior portion of a die using external interconnects are described herein. The approach provides for contacts coupled to circuits in the interior portion of the die, where the contacts are exposed to an exterior portion of the die. The external interconnects are configured to couple these contacts so that signals from the circuits in the interior portion of the die may be routed externally to the die. In various aspects of the disclosed approach, the external interconnects are protected by a packaging for the die.

公开(公告)号：US09324397B1

公开(公告)日：2016-04-26

申请号：US14598528

申请日：2015-01-16

Applicant: QUALCOMM Incorporated

Inventor： Kunal Mukesh Desai ,  Piyush Gupta ,  Bernie Jord Yang ,  Umesh Madhusudan Rao

IPC: G11C7/00 ,  G11C7/22 ,  G11C7/10 ,  G11C8/06 ,  G11C8/18

CPC classification number: G11C7/22 ,  G06F13/1694 ,  G11C7/10 ,  G11C8/06 ,  G11C8/18 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15311 ,  H01L2924/00014

Abstract: A configurable die including a logic element configured to communicate a control and address (CA) signal and a data (DQ) signal, and a first generic physical interface (PHY) and a second generic PHY in communication with the logic element, wherein each of the first generic PHY and the second generic PHY is configurable as a CA PHY and as a DQ PHY, and wherein the logic element is configurable to communicate the CA signal and the DQ signal to different ones of the first and second generic PHYs.

Abstract translation: 一种可配置管芯，包括被配置为传送控制和地址（CA）信号和数据（DQ））信号的逻辑元件，以及与逻辑元件通信的第一通用物理接口（PHY）和第二通用PHY，其中每个 第一通用PHY和第二通用PHY可配置为CA PHY和DQ PHY，并且其中逻辑元件可配置为将CA信号和DQ信号传送到第一和第二通用PHY中的不同PHY。