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    Integrated circuit and code generating method
    1.
    发明授权
    Integrated circuit and code generating method 有权

    公开(公告)号：US10475927B2

    公开(公告)日：2019-11-12

    申请号：US15927088

    申请日：2018-03-21

    Applicant: PHISON ELECTRONICS CORP.

    Inventor： Hiroshi Watanabe

    IPC: G11C8/00 ,  H01L29/78 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/06 ,  H01L29/786 ,  H03K3/84

    Abstract: An integrated circuit and a code generating method are described. The integrated circuit includes a plurality of field effect transistors, a plurality of sense-amplifiers, and a processing circuit. Each field effect transistor is configured to represent an address in a mapping table and includes a source, a drain, a channel and a gate. Each sense-amplifier is connected to the drain and configured to sense an electric current from the drain and identify a threshold voltage of the corresponding field effect transistor. The processing circuit is configured to categorize each of the threshold voltages identified by the corresponding sense-amplifiers into a first state and a second state and mark the state of each of the threshold voltages at the corresponding address in the mapping table.

    NON-VOLATILE MEMORY DEVICE
    3.
    发明申请
    NON-VOLATILE MEMORY DEVICE 审中-公开
    非易失性存储器件

    公开(公告)号：US20150236033A1

    公开(公告)日：2015-08-20

    申请号：US14704982

    申请日：2015-05-06

    Applicant: PHISON ELECTRONICS CORP.

    Inventor： Hiroshi Watanabe

    IPC: H01L27/115

    CPC classification number: H01L21/768 ,  G11C16/0408 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/26 ,  H01L23/5222 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11551 ,  H01L29/788 ,  H01L29/7881

    Abstract: Provided is a non-volatile memory device having a zigzag body wiring. A well is disposed in a substrate. Word lines are arranged in an array, are disposed on the substrate and extend in a first direction. Inter-poly dielectric films are respectively between the substrate and the word lines. Floating gates are respectively disposed between the well and the inter-poly dielectric films. Tunnel oxide films are respectively disposed between the well and the floating gates. First bit lines and second bit lines, arranged periodically, are disposed over the word lines and extend in a second direction, wherein a first distance from the first bit lines to the substrate is smaller than a second distance from the second bit lines to the substrate.

    Abstract translation: 提供了具有锯齿形主体布线的非易失性存储器件。 一个孔设置在基板中。 字线排列成阵列，设置在基板上并沿第一方向延伸。 多晶硅介电膜分别在基板和字线之间。 浮栅分别设置在阱和多晶硅介电膜之间。 隧道氧化膜分别设置在阱和浮栅之间。 布置成周期性排列的第一位线和第二位线被布置在字线之上并沿第二方向延伸，其中从第一位线到基板的第一距离小于从第二位线到基板的第二距离 。

    NON-VOLATILE MEMORY DEVICE AND OPERATION AND FABRICATING METHODS THEREOF
    4.
    发明申请
    NON-VOLATILE MEMORY DEVICE AND OPERATION AND FABRICATING METHODS THEREOF 有权
    非易失性存储器件及其操作及其制作方法

    公开(公告)号：US20150049557A1

    公开(公告)日：2015-02-19

    申请号：US13969626

    申请日：2013-08-19

    Applicant: Phison Electronics Corp.

    Inventor： Hiroshi Watanabe

    IPC: H01L29/788 ,  H01L21/768 ,  G11C16/26 ,  G11C16/14 ,  G11C16/04

    CPC classification number: H01L21/768 ,  G11C16/0408 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/26 ,  H01L23/5222 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11551 ,  H01L29/788 ,  H01L29/7881

    Abstract: Provided is a non-volatile memory device having a zigzag body wiring. First word lines and second word lines are disposed on a substrate, arranged periodically and extended along a first direction. First inter-poly dielectric films are disposed on the substrate and respectively beneath the first word lines. Second inter-poly dielectric films are disposed on the substrate and respectively beneath the second word lines, wherein the first inter-poly dielectric films are thinner than the second inter-poly dielectric films. A floating gate is disposed between the substrate and each of the first and second inter-poly dielectric films. A tunnel oxide film is disposed between the substrate and each of the floating gates. Bit lines are disposed above the first and second word lines and extended along a second direction different from the first direction.

    Abstract translation: 提供了具有锯齿形主体布线的非易失性存储器件。 第一字线和第二字线被布置在基板上，周期性地布置并沿着第一方向延伸。 第一多晶硅介电膜设置在基板上并分别在第一字线下方。 第二多晶硅介电膜设置在基板上并分别在第二字线的下方，其中第一多晶硅介电膜比第二多晶硅介电膜薄。 浮置栅极设置在基板和第一和第二多晶硅间绝缘膜中的每一个之间。 隧道氧化膜设置在衬底和每个浮动栅极之间。 位线设置在第一和第二字线上方并沿着不同于第一方向的第二方向延伸。

    Non-volatile memory device
    5.
    发明授权
    Non-volatile memory device 有权
    非易失性存储器件

    公开(公告)号：US09123578B1

    公开(公告)日：2015-09-01

    申请号：US14704982

    申请日：2015-05-06

    Applicant: PHISON ELECTRONICS CORP.

    Inventor： Hiroshi Watanabe

    IPC: G11C16/16 ,  H01L27/115

    CPC classification number: H01L21/768 ,  G11C16/0408 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/26 ,  H01L23/5222 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11551 ,  H01L29/788 ,  H01L29/7881

    Abstract: Provided is a non-volatile memory device having a zigzag body wiring. A well is disposed in a substrate. Word lines are arranged in an array, are disposed on the substrate and extend in a first direction. Inter-poly dielectric films are respectively between the substrate and the word lines. Floating gates are respectively disposed between the well and the inter-poly dielectric films. Tunnel oxide films are respectively disposed between the well and the floating gates. First bit lines and second bit lines, arranged periodically, are disposed over the word lines and extend in a second direction, wherein a first distance from the first bit lines to the substrate is smaller than a second distance from the second bit lines to the substrate.

    Abstract translation: 提供了具有锯齿形主体布线的非易失性存储器件。 一个孔设置在基板中。 字线排列成阵列，设置在基板上并沿第一方向延伸。 多晶硅介电膜分别在基板和字线之间。 浮栅分别设置在阱和多晶硅介电膜之间。 隧道氧化膜分别设置在阱和浮栅之间。 布置在字线周围的第一位线和第二位线在第二方向上延伸，其中从第一位线到衬底的第一距离小于从第二位线到衬底的第二距离 。

    MEMORY MANAGEMENT METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROLLING CIRCUIT UNIT
    7.
    发明申请
    MEMORY MANAGEMENT METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROLLING CIRCUIT UNIT 有权
    存储器管理方法，存储器存储器和存储器控制电路单元

    公开(公告)号：US20160329103A1

    公开(公告)日：2016-11-10

    申请号：US14702770

    申请日：2015-05-04

    Applicant: PHISON ELECTRONICS CORP.

    Inventor： Hiroshi Watanabe

    IPC: G11C16/14

    CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C2211/5641

    Abstract: A memory management method, a memory storage device and a memory controlling circuit unit are provided. The method comprises: obtaining an erased state voltage of a first memory cell and a programmed state voltage of the first memory cell, where the first memory cell is operated in a first programming mode; and operating the first memory cell in a second programming mode if a width of a gap between the erased state voltage and the programmed state voltage is larger than a first threshold value. Accordingly, the reliability of the first memory cell may be improved.

    Abstract translation: 提供存储器管理方法，存储器存储装置和存储器控制电路单元。 该方法包括：获得第一存储单元的擦除状态电压和第一存储单元的编程状态电压，其中第一存储单元以第一编程模式操作; 以及如果所述擦除状态电压和所述编程状态电压之间的间隙的宽度大于第一阈值，则以第二编程模式操作所述第一存储器单元。 因此，可以提高第一存储单元的可靠性。

    Memory management method, memory storage device and memory control circuit unit
    8.
    发明授权
    Memory management method, memory storage device and memory control circuit unit 有权
    存储器管理方法，存储器件和存储器控制电路单元

    公开(公告)号：US09418731B1

    公开(公告)日：2016-08-16

    申请号：US14934154

    申请日：2015-11-06

    Applicant: PHISON ELECTRONICS CORP.

    Inventor： Hiroshi Watanabe

    IPC: G11C16/00 ,  G11C11/56 ,  G11C16/14 ,  G11C16/04

    CPC classification number: G11C16/08 ,  G11C11/5628 ,  G11C16/0458 ,  G11C2211/5641

    Abstract: A memory management method, a memory storage device and a memory control circuit unit are provided. The method comprises: obtaining a first threshold voltage distribution of memory cells; grouping the first threshold voltage distribution to a plurality of first threshold voltage groups; obtaining a second threshold voltage distribution of the memory cells; grouping the second threshold voltage distribution to a plurality of second threshold voltage groups; allocating a memory cell among the memory cells to a virtual block if a threshold voltage pair of the memory cell belongs to a specific group of the first threshold voltage groups and a specific group of the second threshold voltage groups, such that the first memory cell is operated under a specific-level cell mode. Accordingly, the reliability of memory cells may be improved without significantly sacrificing the capacity of the rewritable non-volatile memory module.

    Abstract translation: 提供存储器管理方法，存储器存储装置和存储器控制电路单元。 该方法包括：获得存储器单元的第一阈值电压分布; 将第一阈值电压分布分组到多个第一阈值电压组; 获得存储器单元的第二阈值电压分布; 将所述第二阈值电压分布分组到多个第二阈值电压组; 如果所述存储单元的阈值电压对属于所述第一阈值电压组的特定组和所述第二阈值电压组的特定组，则将所述存储器单元中的存储器单元分配给虚拟块，使得所述第一存储单元为 在特定级别的单元格模式下运行。 因此，可以提高存储器单元的可靠性，而不会显着地牺牲可重写非易失性存储器模块的容量。

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