公开(公告)号：US08488686B2

公开(公告)日：2013-07-16

申请号：US13152170

申请日：2011-06-02

申请人： Philip Yeung ,  Richard E Perego ,  Scott C Best

发明人： Philip Yeung ,  Richard E Perego ,  Scott C Best

IPC分类号： H04L27/00

CPC分类号： G11C7/20 ,  G11C29/02 ,  G11C29/022 ,  G11C29/028 ,  G11C2029/4402 ,  H04L5/1438 ,  H04L7/0004 ,  H04L7/0091 ,  H04L7/10 ,  H04L25/49

摘要： A communication channel is operated by storing a calibrated parameter value in nonvolatile memory during manufacturing, testing, or during a first operation of the device. Upon starting operation of the communication channel in the field, the calibrated parameter value is obtained from the nonvolatile memory, and used in applying an operating parameter of the communication channel. After applying the operating parameter, communication is initiated on a communication channel. The operating parameter can be adjusted to account for drift immediately after starting up, or periodically. The process of starting operation in the field includes power up events after a power management operation. In embodiments where one component includes memory, steps can be taken prior to a power management operation using the communication channel, such as transferring calibration patterns to be used in calibration procedures.

摘要翻译： 在制造，测试期间或在设备的第一次操作期间，将经校准的参数值存储在非易失性存储器中来操作通信通道。 在现场通信通道开始运行时，从非易失性存储器获得校准参数值，并用于应用通信信道的操作参数。 应用操作参数后，在通信通道上启动通信。 操作参数可以在启动后立即进行调整，或者定期进行。 在现场开始运行的过程包括电源管理操作后的上电事件。 在一个组件包括存储器的实施例中，可以在使用通信信道进行功率管理操作之前采取步骤，例如传送校正过程中使用的校准模式。

公开(公告)号：US07978754B2

公开(公告)日：2011-07-12

申请号：US10857483

申请日：2004-05-28

申请人： Philip Yeung ,  Richard E Perego ,  Scott C Best

发明人： Philip Yeung ,  Richard E Perego ,  Scott C Best

IPC分类号： H04B3/46

CPC分类号： G11C7/20 ,  G11C29/02 ,  G11C29/022 ,  G11C29/028 ,  G11C2029/4402 ,  H04L5/1438 ,  H04L7/0004 ,  H04L7/0091 ,  H04L7/10 ,  H04L25/49

摘要： A communication channel is operated by storing a calibrated parameter value in nonvolatile memory during manufacturing, testing, or during a first operation of the device. Upon starting operation of the communication channel in the field, the calibrated parameter value is obtained from the nonvolatile memory, and used in applying an operating parameter of the communication channel. After applying the operating parameter, communication is initiated on a communication channel. The operating parameter can be adjusted to account for drift immediately after starting up, or periodically. The process of starting operation in the field includes power up events after a power management operation. In embodiments where one component includes memory, steps can be taken prior to a power management operation using the communication channel, such as transferring calibration patterns to be used in calibration procedures.

摘要翻译： 在制造，测试期间或在设备的第一次操作期间，将经校准的参数值存储在非易失性存储器中来操作通信通道。 在现场通信通道开始运行时，从非易失性存储器获得校准参数值，并用于应用通信信道的操作参数。 应用操作参数后，在通信通道上启动通信。 操作参数可以在启动后立即进行调整，或者定期进行。 在现场开始运行的过程包括电源管理操作后的上电事件。 在一个组件包括存储器的实施例中，可以在使用通信信道进行功率管理操作之前采取步骤，例如传送校正过程中使用的校准模式。

公开(公告)号：US08112608B2

公开(公告)日：2012-02-07

申请号：US12631614

申请日：2009-12-04

申请人： Richard E Perego ,  Donald C. Stark ,  Frederick A. Ware ,  Ely K. Tsern ,  Craig E. Hampel

发明人： Richard E Perego ,  Donald C. Stark ,  Frederick A. Ware ,  Ely K. Tsern ,  Craig E. Hampel

IPC分类号： G06F12/08

CPC分类号： G06F13/1678 ,  G06F12/04 ,  G06F12/06 ,  G06F12/0646 ,  G06F13/1657 ,  G06F13/4022 ,  G11C5/02 ,  G11C5/025 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C7/1006 ,  G11C7/1045 ,  G11C7/1048 ,  G11C7/106 ,  G11C7/1072 ,  G11C7/1087 ,  G11C8/06 ,  G11C11/4087 ,  G11C11/4097 ,  G11C2207/105 ,  G11C2207/108 ,  H05K1/117 ,  H05K1/14 ,  H05K2201/09954 ,  H05K2201/10189 ,  Y02D10/14

摘要： Described is a memory system in which the memory core organization changes with device width. The number of physical memory banks accessed reduces with device width, resulting in reduced power usage for relatively narrow memory configurations. Increasing the number of logic memory banks for narrow memory widths reduces the likelihood of bank conflicts, and consequently improves speed performance.

摘要翻译： 描述了存储器系统，其中存储器核心组织随设备宽度而变化。 所访问的物理存储器组的数量随着器件宽度而减少，导致相对较窄的存储器配置的功率消耗减少。 增加用于窄内存宽度的逻辑内存库的数量可以减少存储体冲突的可能性，从而提高速度性能。

公开(公告)号：US07848156B2

公开(公告)日：2010-12-07

申请号：US12055679

申请日：2008-03-26

申请人： Richard E Perego ,  Frederick A Ware

发明人： Richard E Perego ,  Frederick A Ware

IPC分类号： G11C7/00

CPC分类号： G11C7/22 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1087 ,  G11C2207/2281 ,  G11C2207/229

摘要： A memory device, system and method for allowing an early read operation after one or more write operations is provided according to an embodiment of the present invention. The memory device comprises an interface for providing a first write address, a first write data, and a read address. A memory core is coupled to the interface and includes a first memory section having a first data path and a first address path and a second memory section having a second data path and a second address path. In an embodiment of the present invention, the first data and first address path is independent of the second data and second address path. The first write data is provided on the first data path responsive to the first write address being provided on the first address path while a read data is provided on the second data path responsive to the read address being provided on the second address path.

摘要翻译： 根据本发明的实施例，提供了在一个或多个写入操作之后允许早期读取操作的存储器件，系统和方法。 存储器件包括用于提供第一写入地址，第一写入数据和读取地址的接口。 存储器核心耦合到接口并且包括具有第一数据路径和第一地址路径的第一存储器部分和具有第二数据路径和第二地址路径的第二存储器部分。 在本发明的实施例中，第一数据和第一地址路径独立于第二数据和第二地址路径。 响应于在第一地址路径上提供第一写地址而在第一数据路径上提供第一写入数据，同时响应于在第二地址路径上提供的读地址在第二数据路径上提供读数据。

公开(公告)号：US07523248B2

公开(公告)日：2009-04-21

申请号：US12013160

申请日：2008-01-11

申请人： Richard E Perego ,  Stefanos Sidiropoulos ,  Ely Tsern

发明人： Richard E Perego ,  Stefanos Sidiropoulos ,  Ely Tsern

IPC分类号： G06F12/00

CPC分类号： G11C29/028 ,  G06F13/1673 ,  G06F13/1684 ,  G11C5/04 ,  G11C7/10 ,  G11C29/02 ,  G11C29/50012

摘要： A system comprises a controller device, an integrated circuit buffer device and a first and second memory device. A first plurality of signal lines is coupled to the controller device. A second plurality of signal lines is coupled to the first memory device and the integrated circuit buffer device. The second plurality of signal lines carries first address information from the integrated circuit buffer device to the first memory device. A third plurality of signal lines is coupled to the first memory device and the integrated circuit buffer device. The third plurality of signal lines carries first control information from the integrated circuit buffer device to the first memory device. A first signal line is coupled to the first memory device and the integrated circuit buffer device. The first signal line carries a first signal from the integrated circuit buffer device to the first memory device. The first signal synchronizes communication of the first control information from the integrated circuit buffer device to the first memory device.

摘要翻译： 一种系统包括控制器装置，集成电路缓冲装置以及第一和第二存储装置。 第一多个信号线耦合到控制器设备。 第二多个信号线耦合到第一存储器件和集成电路缓冲器件。 第二多个信号线将第一地址信息从集成电路缓冲器装置传送到第一存储器件。 第三组信号线耦合到第一存储器件和集成电路缓冲器件。 第三多个信号线将第一控制信息从集成电路缓冲器装置传送到第一存储器件。 第一信号线耦合到第一存储器件和集成电路缓冲器件。 第一信号线将来自集成电路缓冲器件的第一信号传送到第一存储器件。 第一信号使来自集成电路缓冲器的第一控制信息与第一存储器件的通信同步。

公开(公告)号：US07921245B2

公开(公告)日：2011-04-05

申请号：US12696807

申请日：2010-01-29

申请人： Richard E Perego ,  Frederick A Ware

发明人： Richard E Perego ,  Frederick A Ware

IPC分类号： G06F13/38 ,  G06F13/00

CPC分类号： G06F13/1684

摘要： A memory system with serialized data transfer. The memory system includes within a memory controller and a plurality of memory devices. The memory controller receives a plurality of write data values from a host and outputs the write data values as respective serial streams of bits. Each of the memory devices receives at least one of the serial streams of bits from the memory controller and converts the serial stream of bits to a set of parallel bits for storage.

摘要翻译： 具有序列化数据传输的存储系统。 存储器系统包括在存储器控制器和多个存储器件内。 存储器控制器从主机接收多个写入数据值，并将写入数据值作为相应串行比特流输出。 每个存储器件从存储器控制器接收至少一个串行比特流，并将串行比特流转换为一组并行比特以进行存储。

公开(公告)号：US07095789B2

公开(公告)日：2006-08-22

申请号：US10766765

申请日：2004-01-28

申请人： Frederick A. Ware ,  Richard E Perego ,  Craig E Hampel

发明人： Frederick A. Ware ,  Richard E Perego ,  Craig E Hampel

IPC分类号： H04B3/00 ,  H04B1/38

CPC分类号： H04L1/242 ,  G11C7/04 ,  G11C7/1057 ,  G11C7/1084 ,  G11C29/022 ,  G11C29/025 ,  G11C29/028 ,  G11C2207/2254 ,  H04L7/0091 ,  H04L7/033 ,  H04L7/10 ,  H04L25/0292 ,  H04L25/12 ,  H04L27/00

摘要： A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.

公开(公告)号：US08422568B2

公开(公告)日：2013-04-16

申请号：US13409534

申请日：2012-03-01

申请人： Frederick A. Ware ,  Richard E Perego ,  Craig E. Hampel

发明人： Frederick A. Ware ,  Richard E Perego ,  Craig E. Hampel

IPC分类号： H04L25/00

CPC分类号： H04L7/0016 ,  G11C7/04 ,  G11C2207/2254 ,  H04L7/0087 ,  H04L7/0091 ,  H04L7/033 ,  H04L7/10 ,  H04L25/0292 ,  H04L25/12

摘要： A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.

公开(公告)号：US08351281B2

公开(公告)日：2013-01-08

申请号：US12961395

申请日：2010-12-06

申请人： Richard E Perego ,  Frederick A Ware

发明人： Richard E Perego ,  Frederick A Ware

IPC分类号： G11C7/00

CPC分类号： G11C7/22 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1087 ,  G11C2207/2281 ,  G11C2207/229

摘要： A memory device, system and method for allowing an early read operation after one or more write operations is provided according to an embodiment of the present invention. The memory device comprises an interface for providing a first write address, a first write data, and a read address. A memory core is coupled to the interface and includes a first memory section having a first data path and a first address path and a second memory section having a second data path and a second address path. In an embodiment of the present invention, the first data and first address path is independent of the second data and second address path. The first write data is provided on the first data path responsive to the first write address being provided on the first address path while a read data is provided on the second data path responsive to the read address being provided on the second address path.

摘要翻译： 根据本发明的实施例，提供了在一个或多个写入操作之后允许早期读取操作的存储器件，系统和方法。 存储器件包括用于提供第一写入地址，第一写入数据和读取地址的接口。 存储器核心耦合到接口并且包括具有第一数据路径和第一地址路径的第一存储器部分和具有第二数据路径和第二地址路径的第二存储器部分。 在本发明的实施例中，第一数据和第一地址路径独立于第二数据和第二地址路径。 响应于在第一地址路径上提供第一写地址而在第一数据路径上提供第一写入数据，同时响应于在第二地址路径上提供的读地址在第二数据路径上提供读数据。

公开(公告)号：US07925808B2

公开(公告)日：2011-04-12

申请号：US12116439

申请日：2008-05-07

申请人： Richard E Perego ,  Frederick A Ware

发明人： Richard E Perego ,  Frederick A Ware

IPC分类号： G06F13/38 ,  G06F13/00

CPC分类号： G06F13/1684

摘要： A memory system with serialized data transfer. The memory system includes within a memory controller and a plurality of memory devices. The memory controller receives a plurality of write data values from a host and outputs the write data values as respective serial streams of bits. Each of the memory devices receives at least one of the serial streams of bits from the memory controller and converts the serial stream of bits to a set of parallel bits for storage.