公开(公告)号：US09111608B2

公开(公告)日：2015-08-18

申请号：US14230558

申请日：2014-03-31

Applicant: Scott C. Best

Inventor： Scott C. Best

IPC: G11C7/22 ,  G11C7/10 ,  G06F13/16

CPC classification number: G11C11/4076 ,  G06F13/1689 ,  G11C7/04 ,  G11C7/222

Abstract: A method of operation in a memory controller is disclosed. The method includes receiving a strobe signal having a first phase relationship with respect to first data propagating on a first data line, and a second phase relationship with respect to second data propagating on a second data line. A first sample signal is generated based on the first phase relationship and a second sample signal is generated based on the second phase relationship. The first data signal is received using a first receiver clocked by the first sample signal. The second data signal is received using a second receiver clocked by the second sample signal.

Abstract translation: 公开了一种在存储器控制器中的操作方法。 该方法包括：接收相对于在第一数据线上传播的第一数据具有第一相位关系的选通信号，以及相对于在第二数据线上传播的第二数据的第二相位关系。 基于第一相位关系产生第一采样信号，并且基于第二相位关系生成第二采样信号。 使用由第一采样信号计时的第一接收机接收第一数据信号。 使用由第二采样信号计时的第二接收机接收第二数据信号。

公开(公告)号：US08930740B2

公开(公告)日：2015-01-06

申请号：US12947758

申请日：2010-11-16

Applicant: Jared L. Zerbe ,  Scott C. Best ,  Brian L. Leibowitz

Inventor： Jared L. Zerbe ,  Scott C. Best ,  Brian L. Leibowitz

IPC: G06F1/00 ,  G06F1/08 ,  G06F13/16 ,  G06F1/32

CPC classification number: G06F1/08 ,  G06F1/32 ,  G06F13/1689

Abstract: This disclosure provides for adjustment of memory IO timing using a voltage controlled oscillator (VCO) and a register that generates a VCO control voltage directly used to vary memory IO timing. The register may be externally programmable by a controller and may be located on a memory device (IC, module or other device) or on an external voltage generator, which then provides an adjustable voltage to the memory device. This structure may be used to adjust memory timing so as to achieve a minimum target bitrate and thus minimize frequency of operation to minimize power. In one embodiment, each of several memory devices may be independently adjusted in this way to achieve a mesochronous memory system; in another embodiment, memory devices may be have their timing adjusted in parallel, with all memory devices equal to or greater than a target bitrate. Teachings presented herein provide a way to relax overdesign requirements and “tune” fast-fast and slow-slow devices to effectively operate as typical devices.

Abstract translation: 本公开提供了使用压控振荡器（VCO）和产生直接用于改变存储器IO定时的VCO控制电压的寄存器来调整存储器IO定时。 寄存器可以由控制器在外部进行编程，并且可以位于存储器件（IC，模块或其他器件）或外部电压发生器上，然后外部电压发生器为存储器件提供可调电压。 该结构可以用于调整存储器定时，以便实现最小目标比特率，从而最小化操作频率以最小化功率。 在一个实施例中，可以以这种方式独立地调整多个存储器件中的每一个以实现间同步存储器系统; 在另一个实施例中，存储器设备可以具有并行调整其定时，所有存储器设备等于或大于目标比特率。 本文提供的教学提供了一种放松超设计要求并“调谐”快速和慢速设备以有效地作为典型设备运行的方法。

公开(公告)号：US08756368B2

公开(公告)日：2014-06-17

申请号：US12505438

申请日：2009-07-17

Applicant: Scott C. Best ,  Ely K. Tsern

Inventor： Scott C. Best ,  Ely K. Tsern

IPC: G06F13/00 ,  G06F12/00 ,  G06F13/28 ,  G11C11/406 ,  G06F13/16

CPC classification number: G11C11/406 ,  G06F13/1636 ,  G11C2211/4061

Abstract: A memory controller is disclosed that provides refresh control circuitry to generate first refresh commands directed to a first row of storage cells within a memory device at a first rate. The refresh control circuitry generates second refresh commands directed to a second row of storage cells within the memory device at a second rate. Output circuitry outputs the first and second refresh commands to the memory device.

Abstract translation: 公开了一种存储器控制器，其提供刷新控制电路以第一速率产生定向到存储器设备内的第一行存储单元的第一刷新命令。 刷新控制电路以第二速率产生定向到存储器装置内的第二行存储单元的第二刷新命令。 输出电路将第一和第二刷新命令输出到存储器件。

公开(公告)号：US08208595B2

公开(公告)日：2012-06-26

申请号：US13169901

申请日：2011-06-27

Applicant: Scott C. Best ,  Richard E. Warmke ,  David B. Roberts ,  Frank Lambrecht

Inventor： Scott C. Best ,  Richard E. Warmke ,  David B. Roberts ,  Frank Lambrecht

IPC: H04L7/00

CPC classification number: G11C11/4076 ,  G06F1/10 ,  G11C7/04 ,  G11C7/10 ,  G11C7/1087 ,  G11C7/222 ,  G11C11/4091 ,  G11C2207/107 ,  H03L7/07 ,  H03L7/0814 ,  H04L7/0337

Abstract: An apparatus that reduces sampling errors for data communicated between devices uses phase information acquired from a timing reference signal such as a strobe signal to align a data-sampling signal for sampling a data signal that was sent along with the timing reference signal. The data-sampling signal may be provided by adjustably delaying a clock signal according to the phase information acquired from the strobe signal. The data-sampling signal may also have an improved waveform compared to the timing reference signal, including a fifty percent duty cycle and sharp transitions. The phase information acquired from the timing reference signal may also be used for other purposes, such as aligning received data with a local clock domain, or transmitting data so that it arrives at a remote device in synchronism with a reference clock signal at the remote device.

Abstract translation: 减少设备之间传送的数据的采样误差的装置使用从定时参考信号（例如选通信号）获取的相位信息，以对齐用于采样与定时参考信号一起发送的数据信号的数据采样信号。 可以通过根据从选通信号获取的相位信息可调地延迟时钟信号来提供数据采样信号。 与定时参考信号相比，数据采样信号也可以具有改进的波形，包括百分之五十的占空比和尖锐的转变。 从定时参考信号获取的相位信息也可以用于其他目的，例如将接收的数据与本地时钟域对准，或者发送数据，使得其与远程设备上的参考时钟信号同步到达远程设备 。

公开(公告)号：US20120068360A1

公开(公告)日：2012-03-22

申请号：US13321121

申请日：2010-05-25

Applicant: Scott C. Best

Inventor： Scott C. Best

IPC: H01L23/498

CPC classification number: G06F13/362 ,  G06F13/4068 ,  G11C11/408 ,  G11C11/409 ,  G11C11/4096 ,  G11C14/0018 ,  G11C16/10 ,  G11C16/26 ,  H01L23/48 ,  H01L23/481 ,  H01L23/50 ,  H01L23/60 ,  H01L24/09 ,  H01L25/0652 ,  H01L25/0657 ,  H01L27/0248 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/08145 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06503 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2224/05552 ,  H01L2924/00

Abstract: The semiconductor device system includes multiple stacked substantially identical semiconductor devices each including a first side and an opposing second side. First and second pads are disposed at the first side of the semiconductor device, while third and fourth pads are disposed at the second side of the semiconductor device. First interface circuit is electrically coupled to the first pad and the third pad, while second interface circuit is electrically coupled to the second pad and the fourth pad. The second interface circuit is separate and distinct from the first interface circuit. At least one first semiconductor device of the multiple semiconductor devices is offset from other of the multiple semiconductor devices such that the fourth pad on the first semiconductor device is aligned with, and electrically connected to, the first pad on an adjacent one of the multiple semiconductor devices. In some embodiments, the first pad is associated with a first capacitance, while the second pad is associated with a second capacitance that is smaller than the first capacitance.

Abstract translation: 半导体器件系统包括多个层叠的基本相同的半导体器件，每个半导体器件包括第一侧和相对的第二侧 第一和第二焊盘设置在半导体器件的第一侧，而第三和第四焊盘设置在半导体器件的第二侧。 第一接口电路电耦合到第一焊盘和第三焊盘，而第二接口电路电耦合到第二焊盘和第四焊盘。 第二接口电路与第一接口电路分离并且不同。 多个半导体器件中的至少一个第一半导体器件偏离多个半导体器件中的其它半导体器件，使得第一半导体器件上的第四焊盘与多个半导体器件中相邻的半导体器件上的第一焊盘对准并电连接到第一焊盘 设备。 在一些实施例中，第一焊盘与第一电容相关联，而第二焊盘与小于第一电容的第二电容相关联。

公开(公告)号：US08135890B2

公开(公告)日：2012-03-13

申请号：US12428114

申请日：2009-04-22

Applicant: Steven C. Woo ,  Scott C. Best

Inventor： Steven C. Woo ,  Scott C. Best

IPC: G06F13/00

CPC classification number: E04B2/58 ,  E04B1/24 ,  E04C2/423 ,  G06F13/4243

Abstract: In a system, a memory bus has a first bus segment coupled to a memory controller that includes control logic and a first memory device, a second bus segment coupled to a second memory device, and a switch to selectively couple and decouple the first bus segment and the second bus segment in response to control information from the control logic. Note that the control logic may output control information to the switch to selectively decouple the first bus segment and the second bus segment to effect a change in an electrical length of the memory bus to enable data transfer with respect to the first memory device at a first data rate. Additionally, the control logic may output control information to the switch to selectively couple the first bus segment and the second bus segment to effect another change in the electrical length of the memory bus to enable data transfer with respect to the second memory device at a second data rate that is slower than the first data rate.

Abstract translation: 在系统中，存储器总线具有耦合到存储器控制器的第一总线段，存储器控制器包括控制逻辑和第一存储器件，耦合到第二存储器件的第二总线段以及用于选择性地耦合和去耦合第一总线段 以及响应于来自控制逻辑的控制信息的第二总线段。 注意，控制逻辑可以将控制信息输出到开关以选择性地去耦合第一总线段和第二总线段以实现存储器总线的电长度的改变，以使得能够在第一存储器装置相对于第一存储器件进行数据传送 数据速率。 另外，控制逻辑可以将控制信息输出到开关以选择性地耦合第一总线段和第二总线段，以实现存储器总线的电长度的另一变化，以使得能够在第二存储器装置相对于第二存储器件进行数据传送 数据速率比第一个数据速率慢。

公开(公告)号：US07978754B2

公开(公告)日：2011-07-12

申请号：US10857483

申请日：2004-05-28

Applicant: Philip Yeung ,  Richard E Perego ,  Scott C Best

Inventor： Philip Yeung ,  Richard E Perego ,  Scott C Best

IPC: H04B3/46

CPC classification number: G11C7/20 ,  G11C29/02 ,  G11C29/022 ,  G11C29/028 ,  G11C2029/4402 ,  H04L5/1438 ,  H04L7/0004 ,  H04L7/0091 ,  H04L7/10 ,  H04L25/49

Abstract: A communication channel is operated by storing a calibrated parameter value in nonvolatile memory during manufacturing, testing, or during a first operation of the device. Upon starting operation of the communication channel in the field, the calibrated parameter value is obtained from the nonvolatile memory, and used in applying an operating parameter of the communication channel. After applying the operating parameter, communication is initiated on a communication channel. The operating parameter can be adjusted to account for drift immediately after starting up, or periodically. The process of starting operation in the field includes power up events after a power management operation. In embodiments where one component includes memory, steps can be taken prior to a power management operation using the communication channel, such as transferring calibration patterns to be used in calibration procedures.

Abstract translation: 在制造，测试期间或在设备的第一次操作期间，将经校准的参数值存储在非易失性存储器中来操作通信通道。 在现场通信通道开始运行时，从非易失性存储器获得校准参数值，并用于应用通信信道的操作参数。 应用操作参数后，在通信通道上启动通信。 操作参数可以在启动后立即进行调整，或者定期进行。 在现场开始运行的过程包括电源管理操作后的上电事件。 在一个组件包括存储器的实施例中，可以在使用通信信道进行功率管理操作之前采取步骤，例如传送校正过程中使用的校准模式。

公开(公告)号：US20100073047A1

公开(公告)日：2010-03-25

申请号：US12628547

申请日：2009-12-01

Applicant: Scott C. Best ,  Richard E. Warmke ,  David B. Roberts ,  Frank Lambrecht

Inventor： Scott C. Best ,  Richard E. Warmke ,  David B. Roberts ,  Frank Lambrecht

IPC: H03L7/06

CPC classification number: G11C11/4076 ,  G06F1/10 ,  G11C7/04 ,  G11C7/10 ,  G11C7/1087 ,  G11C7/222 ,  G11C11/4091 ,  G11C2207/107 ,  H03L7/07 ,  H03L7/0814 ,  H04L7/0337

Abstract: An apparatus that reduces sampling errors for data communicated between devices uses phase information acquired from a timing reference signal such as a strobe signal to align a data-sampling signal for sampling a data signal that was sent along with the timing reference signal. The data-sampling signal may be provided by adjustably delaying a clock signal according to the phase information acquired from the strobe signal. The data-sampling signal may also have an improved waveform compared to the timing reference signal, including a fifty percent duty cycle and sharp transitions. The phase information acquired from the timing reference signal may also be used for other purposes, such as aligning received data with a local clock domain, or transmitting data so that it arrives at a remote device in synchronism with a reference clock signal at the remote device.

Abstract translation: 减少设备之间传送的数据的采样误差的装置使用从定时参考信号（例如选通信号）获取的相位信息，以对齐用于采样与定时参考信号一起发送的数据信号的数据采样信号。 可以通过根据从选通信号获取的相位信息可调地延迟时钟信号来提供数据采样信号。 与定时参考信号相比，数据采样信号也可以具有改进的波形，包括百分之五十的占空比和尖锐的转变。 从定时参考信号获取的相位信息也可以用于其他目的，例如将接收的数据与本地时钟域对准，或者发送数据，使得其与远程设备上的参考时钟信号同步到达远程设备 。

公开(公告)号：US07398333B2

公开(公告)日：2008-07-08

申请号：US10899719

申请日：2004-07-21

Applicant: Craig E. Hampel ,  Scott C. Best

Inventor： Craig E. Hampel ,  Scott C. Best

IPC: G06K9/36 ,  G06F1/04 ,  H04L7/02

CPC classification number: H05K1/0248 ,  H05K1/0216 ,  H05K1/0268 ,  H05K2201/09781 ,  H05K2201/10689

Abstract: An integrated circuit input/output interface with empirically determined delay matching is disclosed. In one embodiment, the integrated circuit input/output interface uses empirical information of the signal traces to adjust the transmit/receive clock of each pin of the interface so as to compensate for delay mismatches caused by differences in signal trace lengths. The empirical information, in one embodiment, includes signal flight time of each signal trace, which can be pre-measured or pre-calculated from known signal trace lengths. The empirical information, in another embodiment, includes trace-specific phase offset values calculated from pre-calculated or pre-measured signal flight times or signal trace lengths. In yet another embodiment, a transmitting device generates a set of serially delayed write clocks, which are used to control symbol transmission over signal traces so as to reduce simultaneous switching output noise and ground bound in the transmitting device.

Abstract translation: 公开了具有经验确定的延迟匹配的集成电路输入/输出接口。 在一个实施例中，集成电路输入/输出接口使用信号迹线的经验信息来调整接口的每个引脚的发送/接收时钟，以补偿由信号迹线长度差引起的延迟失配。 在一个实施例中，经验信息包括每个信号迹线的信号飞行时间，其可以从已知信号迹线长度预先测量或预先计算。 在另一个实施例中，经验信息包括从预先计算的或预先测量的信号飞行时间或信号迹线长度计算出的特征相位偏移值。 在另一个实施例中，发送装置产生一组串行延迟的写入时钟，其用于控制​​信号迹线上的符号传输，以便减少发送装置中同时的开关输出噪声和接地限制。

公开(公告)号：US07171321B2

公开(公告)日：2007-01-30

申请号：US10923421

申请日：2004-08-20

Applicant: Scott C. Best

Inventor： Scott C. Best

IPC: G01R35/00

CPC classification number: G11C11/4076 ,  G06F13/1689 ,  G11C7/04 ,  G11C7/222

Abstract: Systems and methods for strobe signal timing calibration and control in strobe-based memory systems are provided below. These strobe-offset control systems and methods receive a strobe signal from a memory device and in turn automatically generate separate per-bit strobe signals for use in receiving data on each data line of a memory system. The systems/methods generate the optimal per-bit strobe signals by automatically calibrating per-bit offset timing between data signals of individual data bits and corresponding strobe signals. The strobe-offset control system effectively removes the detected phase difference between the data signal and the strobe signal.

Abstract translation: 以下提供了基于闪光灯的存储器系统中的选通信号定时校准和控制的系统和方法。 这些选通偏移控制系统和方法从存储器件接收选通信号，并且依次自动产生用于在存储器系统的每个数据线上接收数据的单独的每位选通信号。 系统/方法通过自动校准单个数据位的数据信号和相应的选通信号之间的每位偏移定时，产生最优的每位选通信号。 选通偏移控制系统有效地消除了检测到的数据信号与选通信号之间的相位差。