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    DIE EDGE SEAL EMPLOYING LOW-K DIELECTRIC MATERIAL
    3.
    发明申请
    DIE EDGE SEAL EMPLOYING LOW-K DIELECTRIC MATERIAL 有权
    DIE EDGE密封采用低K电介质材料

    公开(公告)号：US20150371957A1

    公开(公告)日：2015-12-24

    申请号：US14555558

    申请日：2014-11-26

    Applicant: Zhijie Wang ,  Zhigang Bai ,  Jiyong Niu ,  Dehong Ye ,  Huchang Zhang

    Inventor： Zhijie Wang ,  Zhigang Bai ,  Jiyong Niu ,  Dehong Ye ,  Huchang Zhang

    IPC: H01L23/00

    CPC classification number: H01L23/562 ,  H01L21/78 ,  H01L22/34 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor wafer has a multi-stage structure that damps and contains nascent cracks generated during dicing and inhibits moisture penetration into the active region of a die. The wafer includes an array of die regions separated by scribe lanes. The die regions include an active region and a first ring that surrounds the active region. A portion of the first ring includes a low-k dielectric material. A second ring includes a stack of alternating layers of metal and interlayer dielectric (ILD) material. A dummy metal region around the rings includes a stacked dummy metal features and surrounds the active region. A regular or irregular staggered arrangement of saw grid process control (SGPC) features reduces mechanical stress during dicing.

    Abstract translation: 半导体晶片具有多级结构，其能够阻止并包含切割期间产生的新生裂纹并且抑制水分渗透到模具的有源区域。 该晶片包括由划线所隔开的芯片区域阵列。 管芯区域包括有源区和围绕有源区的第一环。 第一环的一部分包括低k电介质材料。 第二环包括金属和层间电介质（ILD）材料的交替层叠。 围绕环的虚设金属区域包括堆叠的虚拟金属特征并围绕有源区域。 锯格过程控制（SGPC）特征的规则或不规则交错排列降低了切割时的机械应力。

    DUAL DIE SEMICONDUCTOR PACKAGE
    5.
    发明申请
    DUAL DIE SEMICONDUCTOR PACKAGE 有权
    双模半导体封装

    公开(公告)号：US20110175212A1

    公开(公告)日：2011-07-21

    申请号：US12830446

    申请日：2010-07-06

    Applicant: Meiquan HUANG ,  Heijin Liu ,  Wenjian Xu ,  Dehong Ye

    Inventor： Meiquan HUANG ,  Heijin Liu ,  Wenjian Xu ,  Dehong Ye

    IPC: H01L23/495 ,  H01L23/34

    CPC classification number: H01L24/49 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49531 ,  H01L23/49575 ,  H01L24/29 ,  H01L24/48 ,  H01L25/0655 ,  H01L2224/2919 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48237 ,  H01L2224/48247 ,  H01L2224/49 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/078 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/0665 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

    Abstract: A dual die semiconductor package has a grid array of electrical contacts on a bottom surface of a substrate. There is a first semiconductor die with a base surface mounted to an upper surface of the substrate and the first semiconductor die has first die upper surface external electrical connection pads on an upper surface that are electrically connected to respective electrical contacts of the grid array. There is also a second semiconductor die with a base surface mounted to an upper surface of a lead frame flag. There are second die upper surface external electrical connection pads on an upper surface of the second semiconductor die. The dual die semiconductor package includes leads and at least some of the leads are electrically connected to respective pads that provide the second die upper surface external electrical connection pads. A package body at encloses the first semiconductor die and the second semiconductor die. The electrical contacts of the grid array and part of each of the leads protrude from the package body to form external package electrical connections. Also, at least part of a base surface of the lead frame flag directly under the second semiconductor die is left exposed by the package body and provides a heat sink.

    Abstract translation: 双模半导体封装在基板的底表面上具有电触点的格栅阵列。 存在第一半导体管芯，其具有安装到基板的上表面的基面，并且第一半导体管芯具有电连接到栅格阵列的各个电触点的上表面上的第一管芯上表面外部电连接焊盘。 还有第二半导体管芯，其基面安装在引线框标志的上表面。 在第二半导体管芯的上表面上具有第二管芯上表面外部电连接焊盘。 双模半导体封装包括引线，并且至少一些引线电连接到提供第二管芯上表面外部电连接焊盘的相应焊盘。 封装体包围第一半导体管芯和第二半导体管芯。 栅格阵列的电触点和每个引线的一部分从封装主体突出以形成外部封装电连接。 此外，直接位于第二半导体管芯下方的引线框标志的基面的至少一部分被封装体暴露并提供散热器。

    Dual die semiconductor package
    8.
    发明授权
    Dual die semiconductor package 有权
    双模半导体封装

    公开(公告)号：US08288847B2

    公开(公告)日：2012-10-16

    申请号：US12830446

    申请日：2010-07-06

    Applicant: Meiquan Huang ,  Hejin Liu ,  Wenjian Xu ,  Dehong Ye

    Inventor： Meiquan Huang ,  Hejin Liu ,  Wenjian Xu ,  Dehong Ye

    IPC: H01L23/02

    CPC classification number: H01L24/49 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49531 ,  H01L23/49575 ,  H01L24/29 ,  H01L24/48 ,  H01L25/0655 ,  H01L2224/2919 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48237 ,  H01L2224/48247 ,  H01L2224/49 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/078 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/0665 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

    Abstract: A dual die semiconductor package has a grid array of electrical contacts on a bottom surface of a substrate. There is a first semiconductor die with a base surface mounted to an upper surface of the substrate and the first semiconductor die has first die upper surface external electrical connection pads on an upper surface that are electrically connected to respective electrical contacts of the grid array. There is also a second semiconductor die with a base surface mounted to an upper surface of a lead frame flag. There are second die upper surface external electrical connection pads on an upper surface of the second semiconductor die. The dual die semiconductor package includes leads and at least some of the leads are electrically connected to respective pads that provide the second die upper surface external electrical connection pads. A package body at encloses the first semiconductor die and the second semiconductor die. The electrical contacts of the grid array and part of each of the leads protrude from the package body to form external package electrical connections. Also, at least part of a base surface of the lead frame flag directly under the second semiconductor die is left exposed by the package body and provides a heat sink.

    Abstract translation: 双模半导体封装在基板的底表面上具有电触点的格栅阵列。 存在第一半导体管芯，其具有安装到基板的上表面的基面，并且第一半导体管芯具有电连接到栅格阵列的相应电触点的上表面上的第一管芯上表面外部电连接焊盘。 还有第二半导体管芯，其基面安装在引线框标志的上表面。 在第二半导体管芯的上表面上具有第二管芯上表面外部电连接焊盘。 双模半导体封装包括引线，并且至少一些引线电连接到提供第二管芯上表面外部电连接焊盘的相应焊盘。 封装体包围第一半导体管芯和第二半导体管芯。 栅格阵列的电触点和每个引线的一部分从封装主体突出以形成外部封装电连接。 此外，直接位于第二半导体管芯下方的引线框标志的基面的至少一部分被封装体暴露并提供散热器。

    Die edge seal employing low-K dielectric material
    9.
    发明授权
    Die edge seal employing low-K dielectric material 有权
    使用低K电介质材料的密封边缘密封

    公开(公告)号：US09406625B2

    公开(公告)日：2016-08-02

    申请号：US14555558

    申请日：2014-11-26

    Applicant: Zhijie Wang ,  Zhigang Bai ,  Jiyong Niu ,  Dehong Ye ,  Huchang Zhang

    Inventor： Zhijie Wang ,  Zhigang Bai ,  Jiyong Niu ,  Dehong Ye ,  Huchang Zhang

    IPC: H01L23/544 ,  H01L27/118 ,  H01L41/338 ,  H01L23/00 ,  H01L23/58 ,  H01L21/78 ,  H01L21/66

    CPC classification number: H01L23/562 ,  H01L21/78 ,  H01L22/34 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor wafer has a multi-stage structure that damps and contains nascent cracks generated during dicing and inhibits moisture penetration into the active region of a die. The wafer includes an array of die regions separated by scribe lanes. The die regions include an active region and a first ring that surrounds the active region. A portion of the first ring includes a low-k dielectric material. A second ring includes a stack of alternating layers of metal and interlayer dielectric (ILD) material. A dummy metal region around the rings includes a stacked dummy metal features and surrounds the active region. A regular or irregular staggered arrangement of saw grid process control (SGPC) features reduces mechanical stress during dicing.

    Abstract translation: 半导体晶片具有多级结构，其能够阻止并包含切割期间产生的新生裂纹并且抑制水分渗透到模具的有源区域。 该晶片包括由划线所隔开的芯片区域阵列。 管芯区域包括有源区和围绕有源区的第一环。 第一环的一部分包括低k电介质材料。 第二环包括金属和层间电介质（ILD）材料的交替层叠。 围绕环的虚设金属区域包括堆叠的虚拟金属特征并围绕有源区域。 锯格过程控制（SGPC）特征的规则或不规则交错排列降低了切割时的机械应力。

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