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公开(公告)号：US09225507B1
公开(公告)日：2015-12-29
申请号：US13910016
申请日：2013-06-04
申请人： PMC-SIERRA US, INC.
CPC分类号： G04F10/005 , G04F10/00 , G06F1/12 , H03L7/0805 , H03L7/087 , H03L7/1976 , H03L7/23 , H03L7/235 , H03M1/00 , H03M1/12 , H03M1/1255 , H03M2201/4233 , H04L7/0331
摘要： Provided is a method and apparatus for aligning a first local oscillator (LO) clock generated by a controllable LO clock generator in a first radio frequency (RF) path with a second LO clock in a second RF path. The apparatus includes a synchronization channel configured to exchange a synchronization clock between the first and second RF paths, a phase detector configured to measure a phase alignment between the first and second LO clocks, and a loop filter configured to drive the controllable LO clock generators using the phase alignment. Also provided is a time to digital converter. The time to digital converter includes a D flip-flop for sampling first and second input clocks with a third clock, and a counter configured to synchronously increment the resulting samples and create a digital proportional value representing the delay between the first and second clocks.
摘要翻译： 提供了一种用于使由第一射频（RF）路径中的可控LO时钟发生器产生的第一本地振荡器（LO）时钟与第二RF路径中的第二LO时钟对准的方法和装置。 该装置包括被配置为在第一和第二RF路径之间交换同步时钟的同步信道，被配置为测量第一和第二LO时钟之间的相位对准的相位检测器，以及被配置为使用 相位对准。 还提供了一个时间到数字转换器。 数字转换器的时间包括用于以第三时钟对第一和第二输入时钟进行采样的D触发器，以及被配置为同步地增加所得样本并产生表示第一和第二时钟之间的延迟的数字比例值的计数器。
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公开(公告)号：US08773296B1
公开(公告)日：2014-07-08
申请号：US13624719
申请日：2012-09-21
申请人： PMC-Sierra US, Inc.
发明人： Tomas Dusatko , William Michael Lye
IPC分类号： H03M1/66
CPC分类号： H03M3/50 , H03M7/3042
摘要： A method and apparatus for interleaving high-speed, delta-sigma based over-sampled DACs. A delta-sigma modulator is decomposed into a parallel poly-phase block-filter running at a lower rate. The generated parallel digital data is then fed directly to the analog DAC output stage where it is directly combined to form the full-rate signal using a 1-hot-of-N output stage. By using a poly-phase implementation, the complexity of the high-speed parallel digital-analog timing interface is simplified, along with the timing requirements of the delta-sigma modulator which normally would have to run at the full-oversampled rate. The 1-hot-of-N signal encoding is directly generated from the parallel delta-sigma modulator, and efficiently encodes the data in such a way to minimize signal-dependent supply noise. The architecture disclosed is advantageous for the practical implementation of high-speed over-sampled DACs, such as those used in stringent wireless applications.
摘要翻译： 一种用于交错高速，基于Δ-Σ的过采样DAC的方法和装置。 Δ-Σ调制器被分解成以较低速率运行的平行多相阻塞滤波器。 然后将所产生的并行数字数据直接馈送到模拟DAC输出级，直接组合以形成全速率信号，使用1-N输出级。 通过使用多相实现，简化了高速并行数模模拟定时接口的复杂性，以及通常必须以全过采样速率运行的Δ-Σ调制器的时序要求。 从并行Δ-Σ调制器直接产生1-N信号编码，并且以这样一种方式有效地对数据进行编码，以最小化信号相关的电源噪声。 所公开的架构对于高速过采样DAC（例如在严格无线应用中使用的那些）的实际实现是有利的。
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公开(公告)号：US09413394B1
公开(公告)日：2016-08-09
申请号：US14676142
申请日：2015-04-01
申请人： PMC-SIERRA US, INC.
发明人： William Michael Lye , John B. Groe
CPC分类号： H03M1/662 , H03F1/02 , H03F3/24 , H03M1/742 , H04B1/0014 , H04B1/0025 , H04B1/0475 , H04B2001/045
摘要： An Interleaved Radio Frequency Digital-to-Analog Converter (RF DAC) suitable for use in cellular base stations and optimized to give both a wide RF tuning range and a wide RF bandwidth is disclosed. The RF DAC uses two levels of interleaving, the first providing a direct conversion path from Base Band (BB) to RF, and the second providing a variable interleaving factor through the use of summation to optimize the output bandwidth as a function of the RF center frequency. Digital Interpolation, including an arbitrary sample rate conversion filter, allows the RF DAC to operate from a wide range of possible BB sample rates and the DAC sample rate is a fixed ratio of the RF center frequency. As a result, the spurious outputs from the RF DAC are in known locations that are relatively easy to filter out, minimizing the frequency planning tasks required for a complete RF system design.
摘要翻译： 公开了适用于蜂窝基站并被优化以提供宽RF调谐范围和宽RF带宽的交错射频数模转换器（RF DAC）。 RF DAC使用两级交织，首先提供从基带（BB）到RF的直接转换路径，第二级通过使用求和来提供可变交织因子，以将作为RF中心的函数的输出带宽进行优化 频率。 数字插值（包括任意采样率转换滤波器）允许RF DAC从宽范围的可能BB采样速率进行工作，DAC采样率是RF中心频率的固定比率。 结果，来自RF DAC的杂散输出处于相对易于滤除的已知位置，从而最小化完整RF系统设计所需的频率规划任务。
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4.发明授权Low-noise flexible frequency clock generation from two fixed-frequency references 有权由两个固定频率参考产生的低噪声灵活频率时钟公开(公告)号：US09112517B1
公开(公告)日：2015-08-18
申请号：US14295742
申请日：2014-06-04
申请人： PMC-SIERRA US, INC.
CPC分类号： H03L7/07 , H03L7/087 , H03L7/099 , H03L7/185 , H03L7/1974 , H03L7/1976 , H03L7/23 , H03L7/235 , H03L2207/12 , H04L7/0025 , H04L7/0331 , H04L7/0332
摘要： A number of methods and clock generator units are disclosed to produce low Phase Noise clocks for use in Radio Frequency systems. The methods and clock generator units all use two reference clocks: a frequency-accurate reference that has comparatively high Phase Noise, and a frequency-inaccurate reference such as that from a BAW or MEMS clock source that has comparatively low Phase Noise. By combining multiple Phase-Locked Loops and a mixer, it is possible to produce flexible output frequencies whose frequency accuracy is derived from the first reference clock but whose Phase Noise level is derived from the second reference clock, all in a readily-integrated and relatively low-cost system.
摘要翻译： 公开了一些方法和时钟发生器单元，以产生用于射频系统的低相位噪声时钟。 方法和时钟发生器单元都使用两个参考时钟：具有相对较高相位噪声的频率精确参考，以及诸如来自具有相对较低相位噪声的BAW或MEMS时钟源的频率不准确的参考。 通过组合多个锁相环和混频器，可以产生灵活的输出频率，其频率精度来自第一参考时钟，但其相位噪声电平来自第二参考时钟，全部以易于集成的和相对的 低成本系统。
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公开(公告)号：US09215062B1
公开(公告)日：2015-12-15
申请号：US14791319
申请日：2015-07-03
申请人： PMC-SIERRA US, INC.
CPC分类号： H03L7/07 , H03L7/087 , H03L7/099 , H03L7/185 , H03L7/1974 , H03L7/1976 , H03L7/23 , H03L7/235 , H03L2207/12 , H04L7/0025 , H04L7/0331 , H04L7/0332
摘要： A number of methods and clock generator units are disclosed to produce low Phase Noise clocks for use in Radio Frequency systems. The methods and clock generator units all use two reference clocks: a frequency-accurate reference that has comparatively high Phase Noise, and a frequency-inaccurate reference such as that from a BAW or MEMS clock source that has comparatively low Phase Noise. By combining multiple Phase-Locked Loops and a mixer, it is possible to produce flexible output frequencies whose frequency accuracy is derived from the first reference clock but whose Phase Noise level is derived from the second reference clock, all in a readily-integrated and relatively low-cost system.
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公开(公告)号：US09231600B1
公开(公告)日：2016-01-05
申请号：US14791321
申请日：2015-07-03
申请人： PMC-SIERRA US, INC.
CPC分类号： H03L7/07 , H03L7/087 , H03L7/099 , H03L7/185 , H03L7/1974 , H03L7/1976 , H03L7/23 , H03L7/235 , H03L2207/12 , H04L7/0025 , H04L7/0331 , H04L7/0332
摘要： A number of methods and clock generator units are disclosed to produce low Phase Noise clocks for use in Radio Frequency systems. The methods and clock generator units all use two reference clocks: a frequency-accurate reference that has comparatively high Phase Noise, and a frequency-inaccurate reference such as that from a BAW or MEMS clock source that has comparatively low Phase Noise. By combining multiple Phase-Locked Loops and a mixer, it is possible to produce flexible output frequencies whose frequency accuracy is derived from the first reference clock but whose Phase Noise level is derived from the second reference clock, all in a readily-integrated and relatively low-cost system.
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公开(公告)号：US09124287B1
公开(公告)日：2015-09-01
申请号：US14580099
申请日：2014-12-22
申请人： PMC-SIERRA US, INC.
发明人： Stanley Ho , William Michael Lye
IPC分类号： H03M1/10 , H03M1/66 , G01R31/3167 , H03M1/06 , H03M7/02
CPC分类号： G01R31/3167 , H03M1/0673 , H03M1/109 , H03M1/66 , H03M7/02 , H03M7/165 , H03M7/22
摘要： An apparatus comprising a scrambler having a plurality of scrambler inputs and 2N scrambler outputs, and a unary-weighted digital to analog converter (DAC) connected to scrambler to generate an analog output signal based on the 2N scrambler outputs. The scrambler has N unique scrambling stages arranged in order between the scrambler inputs and the scrambler outputs from a first scrambling stage to a last scrambling stage. Each of the N unique scrambling stages has a plurality of stage inputs and outputs, with the stage inputs of the first scrambling stage connected to the scrambler inputs, the stage outputs of each scrambling stage except the last scrambling stage connected to the stage inputs of a next scrambling stage, and the stage outputs of the last scrambling stage connected to the scrambler outputs. Each of the N unique scrambling stages is operable to pass signals at the inputs to the outputs in either an unscrambled or scrambled state under control of a control bit provided by an N-bit entropy signal. When an N+1 bit input signal is applied to the scrambler inputs and the N-bit entropy signal is randomized the analog output signal from the DAC has improved linearity compared to the analog output signal generated from a non-scrambled input, and when a test input signal is applied to the scrambler inputs and the entropy signal is swept through 2N orthogonal values the analog output signal from the DAC indicates whether a fault exists in one of the scrambler and the DAC.
摘要翻译： 一种包括具有多个加扰器输入和2N个加扰器输出的加扰器的装置，以及连接到加扰器的一次加密数模转换器（DAC），以基于2N个加扰器输出产生模拟输出信号。 加扰器具有N个唯一的加扰阶段，其按扰频器输入和从第一加扰阶段到最后加扰阶段的加扰器输出之间的顺序排列。 N个唯一加扰阶段中的每一个具有多个级输入和输出，其中第一加扰级的级输入连接到加扰器输入，除了与第一加扰级相连的第一加扰级之外的每个加扰级的级输出 下一个加扰阶段，以及连接到加扰器输出的最后一个加扰级的级输出。 N个唯一加扰级中的每一个可操作以在由N位熵信号提供的控制位的控制下以未加扰或加扰状态将输入处的信号传递到输出。 当将N + 1位输入信号施加到扰频器输入并且N位熵信号被随机化时，与从非加扰输入产生的模拟输出信号相比，来自DAC的模拟输出信号具有改善的线性度，并且当 测试输入信号被施加到加扰器输入，并且熵信号通过2N个正交值扫描，来自DAC的模拟输出信号指示在扰频器和DAC之一中是否存在故障。
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公开(公告)号：US09094033B1
公开(公告)日：2015-07-28
申请号：US14604024
申请日：2015-01-23
申请人： PMC-SIERRA US, INC.
发明人： William Michael Lye
CPC分类号： H03M1/68 , H03M1/00 , H03M1/0626 , H03M1/747
摘要： A device that performs Quantization Noise-Shaping and operates at high clock rates. The device can be implemented in parallel with large parallelization factors to produce extremely high throughput. The device has two feed-forward filters that can be implemented using standard parallel Digital Signal Processing techniques. The device can be used in various systems such as Digital-to-Analog Converter (DAC) system and Fractional-N frequency synthesis systems.
摘要翻译： 一种执行量化噪声整形并以高时钟速率工作的器件。 该装置可以与大并行化因素并行实现，以产生极高的吞吐量。 该器件具有两个可以使用标准并行数字信号处理技术实现的前馈滤波器。 该器件可用于各种系统，例如数模转换器（DAC）系统和分数N频率合成系统。
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公开(公告)号：US09225508B1
公开(公告)日：2015-12-29
申请号：US14791329
申请日：2015-07-03
申请人： PMC-SIERRA US, INC.
CPC分类号： H03L7/07 , H03L7/087 , H03L7/099 , H03L7/185 , H03L7/1974 , H03L7/1976 , H03L7/23 , H03L7/235 , H03L2207/12 , H04L7/0025 , H04L7/0331 , H04L7/0332
摘要： A number of methods and clock generator units are disclosed to produce low Phase Noise clocks for use in Radio Frequency systems. The methods and clock generator units all use two reference clocks: a frequency-accurate reference that has comparatively high Phase Noise, and a frequency-inaccurate reference such as that from a BAW or MEMS clock source that has comparatively low Phase Noise. By combining multiple Phase-Locked Loops and a mixer, it is possible to produce flexible output frequencies whose frequency accuracy is derived from the first reference clock but whose Phase Noise level is derived from the second reference clock, all in a readily-integrated and relatively low-cost system.
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