公开(公告)号：US10446694B2

公开(公告)日：2019-10-15

申请号：US15620846

申请日：2017-06-13

Applicant: National Applied Research Laboratories

Inventor： Kai-Shin Li ,  Bo-Wei Wu ,  Min-Cheng Chen ,  Jia-Min Shieh ,  Wen-Kuan Yeh

IPC: H01L29/786 ,  H01L29/08 ,  H01L29/06 ,  H01L29/24 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/423 ,  H01L29/778 ,  H01L29/10

Abstract: A field-effect transistor structure having two-dimensional transition metal dichalcogenides includes a substrate, a source/drain structure, a two-dimensional (2D) channel layer, and a gate layer. The source/drain structure is disposed on the substrate and has a surface higher than a surface of the substrate. The 2D channel layer is disposed on the source and the drain and covers the space between the source and the drain. The gate layer is disposed between the source and the drain and covers the 2D channel layer. The field-effect transistor having two-dimensional transition metal dichalcogenides is a planar field-effect transistor or a fin field-effect transistor.

公开(公告)号：US20140131716A1

公开(公告)日：2014-05-15

申请号：US13744594

申请日：2013-01-18

Applicant: NATIONAL APPLIED RESEARCH LABORATORIES

Inventor： Jia-Min Shieh ,  Yu-Chung Lien ,  Wen-Hsien Huang ,  Chang-Hong Shen ,  Min-Cheng Chen ,  Ci-Ling Pan

IPC: H01L29/792

CPC classification number: H01L29/66825 ,  B82Y40/00 ,  H01L29/40114 ,  H01L29/42332 ,  H01L29/7881 ,  Y10S977/774

Abstract: A memory device comprises a substrate, a tunnel oxide layer, a charge trapping layer, a block oxide layer, a plurality of conductive quantum dots, a metal gate and a source/drain structure. The tunnel oxide layer is disposed on the substrate and has a thickness substantially less than or equal to 2 nm. The charge trapping layer is disposed on the tunnel oxide layer. The quantum dots are embedded in the charge trapping layer. The block oxide layer is disposed on the charge trapping layer. The metal gate essentially consisting of aluminum (Al), copper (Cu), tantalum nitride (TiN), titanium nitride (TaN), aluminum-silicon-copper (Al—Si—Cu) alloys or the arbitrary combinations thereof is disposed on the block oxide layer. The source/drain structure is disposed in the substrate.

Abstract translation: 存储器件包括衬底，隧道氧化物层，电荷俘获层，块状氧化物层，多个导电量子点，金属栅极和源极/漏极结构。 隧道氧化物层设置在基板上，其厚度基本上小于或等于2nm。 电荷捕获层设置在隧道氧化物层上。 量子点嵌入电荷俘获层中。 块状氧化物层设置在电荷俘获层上。 基本上由铝（Al），铜（Cu），氮化钽（TiN），氮化钛（TaN），铝 - 硅 - 铜（Al-Si-Cu）合金或其任意组合组成的金属栅极设置在 块状氧化物层。 源极/漏极结构设置在衬底中。

公开(公告)号：US08987071B2

公开(公告)日：2015-03-24

申请号：US14107742

申请日：2013-12-16

Applicant: National Applied Research Laboratories

Inventor： Min-Cheng Chen ,  Chang-Hsien Lin ,  Chia-Yi Lin ,  Tung-Yen Lai ,  Chia-Hua Ho

IPC: H01L27/12 ,  H01L29/06 ,  B82Y10/00 ,  H01L27/06 ,  H01L21/84 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L27/127 ,  B82Y10/00 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/0665 ,  H01L29/0676

Abstract: A thin-film transistor comprises a semiconductor panel, a dielectric layer, a semiconductor film layer, a conduct layer, a source and a drain. The semiconductor panel comprises a base, an intra-dielectric layer, at least one metal wire layer and at least one via layer. The dielectric layer is stacked on the semiconductor panel. The semiconductor film layer is stacked on the dielectric layer. The conduct layer is formed on the semiconductor film layer. The source is formed on the via of the vias that is adjacent to and connects to the gate via. The drain is formed on another via of the vias that is adjacent to and connects to the gate via. A fabricating method for a thin-film transistor with metal-gates and nano-wires is also disclosed.

Abstract translation: 薄膜晶体管包括半导体板，电介质层，半导体膜层，导电层，源极和漏极。 半导体面板包括基底，介质内介质层，至少一个金属线层和至少一个通孔层。 电介质层堆叠在半导体面板上。 半导体膜层层叠在电介质层上。 导电层形成在半导体膜层上。 源极形成在与通孔相邻并连接到通孔的通孔的通孔上。 漏极形成在邻近并连接到栅极通孔的通孔的另一个通孔上。 还公开了一种具有金属栅极和纳米线的薄膜晶体管的制造方法。

公开(公告)号：US20180358474A1

公开(公告)日：2018-12-13

申请号：US15620846

申请日：2017-06-13

Applicant: National Applied Research Laboratories

Inventor： Kai-Shin Li ,  Bo-Wei Wu ,  Min-Cheng Chen ,  Jia-Min Shieh ,  Wen-Kuan Yeh

IPC: H01L29/786 ,  H01L29/08 ,  H01L29/06 ,  H01L29/24 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/78696 ,  H01L21/02697 ,  H01L29/0657 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/24 ,  H01L29/42356 ,  H01L29/66969 ,  H01L29/778 ,  H01L29/785 ,  H01L29/78603 ,  H01L29/78618

Abstract: A field-effect transistor structure having two-dimensional transition metal dichalcogenides includes a substrate, a source/drain structure, a two-dimensional (2D) channel layer, and a gate layer. The source/drain structure is disposed on the substrate and has a surface higher than a surface of the substrate. The 2D channel layer is disposed on the source and the drain and covers the space between the source and the drain. The gate layer is disposed between the source and the drain and covers the 2D channel layer. The field-effect transistor having two-dimensional transition metal dichalcogenides is a planar field-effect transistor or a fin field-effect transistor.