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公开(公告)号：US11811317B2
公开(公告)日：2023-11-07
申请号：US17303129
申请日：2021-05-20
申请人： NXP B.V.
CPC分类号： H02M3/157 , H02M1/0025
摘要： A controller for controlling a DC-DC converter in a discontinuous conduction mode (DCM) includes an output module configured to provide a switch control signal to the DC-DC converter having an on-time and a switching frequency. The controller includes an on-time-control-module configured to receive a first compensation signal based on the output voltage of the DC-DC converter; and set the on-time of the switch control signal based on the first compensation signal. The controller also includes a frequency-control-module configured to receive a second compensation signal, wherein the second compensation signal is based on the output voltage of the DC-DC converter, and regulate the second compensation signal to a target range by setting the switching frequency of the switch control signal to one of a plurality of pre-defined discrete switching frequencies.
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公开(公告)号：US11621625B2
公开(公告)日：2023-04-04
申请号：US17303127
申请日：2021-05-20
申请人： NXP B.V.
摘要： A burst-mode controller for a DC-DC converter includes an output module configured to provide a switch control signal to the DC-DC converter. The switch control signal includes a plurality of burst windows, each burst window corresponding to a period of a fixed-frequency burst clock and having a number of switching cycles. The burst-mode controller includes an on-time-control-module configured to receive a compensation signal based on the output voltage of the DC-DC converter, and set an on-time of the switching cycles of the switch control signal based on the compensation signal. The burst-mode controller also includes a burst-control-module configured to regulate the on-time of the switching cycles of the switch control signal by setting the number of switching cycles for each burst window of the switch control signal.
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公开(公告)号：US20160094218A1
公开(公告)日：2016-03-31
申请号：US14835403
申请日：2015-08-25
申请人： NXP B.V.
IPC分类号： H03K17/687
CPC分类号： H03K17/687 , H03K17/04206 , H03K17/102 , H03K17/163 , H03K17/6871 , H03K2017/6875 , H03K2217/0081
摘要： A cascode transistor circuit comprising a depletion-mode switch in series with a normally-off switch between a drain output terminal and a source output terminal. The circuit also includes a controller comprising a controller output terminal configured to provide a normally-on control signal for a normally-on control terminal of the depletion-mode switch, wherein the normally-on control signal is independent of the normally-off control signal; a negative voltage source configured to provide a negative voltage to the normally-on control terminal of the depletion-mode switch; and a feedback capacitance between the drain output terminal and a control node in a circuit path between the controller output terminal and the normally-on control terminal of the depletion-mode switch.
摘要翻译： 一种共源共栅晶体管电路，包括与漏极输出端子和源极输出端子之间的常关断开串联的耗尽型开关。 该电路还包括控制器，该控制器包括控制器输出端子，该控制器输出端子被配置为为耗尽型开关的常开控制端提供常开控制信号，其中常开控制信号独立于常关控制信号 ; 负电压源，被配置为向所述耗尽型开关的常开控制端子提供负电压; 以及在所述控制器输出端子与所述耗尽型开关的常开控制端子之间的电路路径中的所述漏极输出端子与所述控制节点之间的反馈电容。
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4.发明授权公开(公告)号：US11940832B2
公开(公告)日：2024-03-26
申请号：US17452602
申请日：2021-10-28
申请人： NXP B.V.
发明人： Matthias Rose , Maxim Kulesh , Neha Goel
IPC分类号： G05F3/30
CPC分类号： G05F3/30
摘要： A first error is determined between a bandgap reference output voltage of a bandgap reference circuit at a first temperature and a target voltage. A second temperature of the bandgap reference circuit is measured. A bandgap reference output voltage of the bandgap reference circuit is predicted at the second temperature and based on the first error. A second error is determined between the bandgap reference output voltage and the target voltage. A trim parameter of the bandgap reference circuit is determined based on the second error. The bandgap reference circuit is set with the trim parameter, where a third error between a bandgap reference output voltage of the bandgap reference with the trim parameter is less than the second error.
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5.发明申请公开(公告)号：US20230139554A1
公开(公告)日：2023-05-04
申请号：US17452602
申请日：2021-10-28
申请人： NXP B.V.
发明人： Matthias Rose , Maxim Kulesh , Neha Goel
IPC分类号： G05F3/30
摘要： A first error is determined between a bandgap reference output voltage of a bandgap reference circuit at a first temperature and a target voltage. A second temperature of the bandgap reference circuit is measured. A bandgap reference output voltage of the bandgap reference circuit is predicted at the second temperature and based on the first error. A second error is determined between the bandgap reference output voltage and the target voltage. A trim parameter of the bandgap reference circuit is determined based on the second error. The bandgap reference circuit is set with the trim parameter, where a third error between a bandgap reference output voltage of the bandgap reference with the trim parameter is less than the second error.
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公开(公告)号：US20210384826A1
公开(公告)日：2021-12-09
申请号：US17303129
申请日：2021-05-20
申请人： NXP B.V.
摘要： A controller for controlling a DC-DC converter in a discontinuous conduction mode (DCM) includes an output module configured to provide a switch control signal to the DC-DC converter having an on-time and a switching frequency. The controller includes an on-time-control-module configured to receive a first compensation signal based on the output voltage of the DC-DC converter; and set the on-time of the switch control signal based on the first compensation signal. The controller also includes and a frequency-control-module configured to receive a second compensation signal, wherein the second compensation signal is based on the output voltage of the DC-DC converter and regulate the second compensation signal to a target range by setting the switching frequency of the switch control signal to one of a plurality of pre-defined discrete switching frequencies.
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公开(公告)号：US10181849B1
公开(公告)日：2019-01-15
申请号：US15825797
申请日：2017-11-29
申请人： NXP B.V.
IPC分类号： G05F3/26 , H03K17/687 , H02M3/07
摘要： A control circuit provides a signal to a control terminal of the transistor to control the conductivity of the transistor. The control circuit includes a voltage-to-current converter that provides an indication of the control terminal-to-current terminal voltage of a transistor. The control circuit includes control circuitry that uses the indication from the voltage-to-current converter in controlling the current applied to the control terminal.
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公开(公告)号：US20170062419A1
公开(公告)日：2017-03-02
申请号：US15233785
申请日：2016-08-10
申请人： NXP B.V.
发明人： Matthias Rose , Jan Sonsky
IPC分类号： H01L27/088 , H01L29/16 , H02M3/158 , H01L29/872 , H01L21/8236 , H01L29/20 , H01L27/02
CPC分类号： H01L27/0883 , H01L21/8236 , H01L27/0255 , H01L29/1608 , H01L29/2003 , H01L29/42316 , H01L29/513 , H01L29/778 , H01L29/872 , H02M3/158 , H03K17/6871
摘要： A semiconductor device comprising: a die-source-terminal, a die-drain-terminal and a die-gate-terminal; a semiconductor-die; an insulated-gate-depletion-mode-transistor provided on the semiconductor-die, the insulated-gate-depletion-mode-transistor comprising a depletion-source-terminal, a depletion-drain-terminal and a depletion-gate-terminal, wherein the depletion-drain-terminal is coupled to the die-drain-terminal and the depletion-gate-terminal is coupled to the die-source-terminal; an enhancement-mode-transistor comprising an enhancement-source-terminal, an enhancement-drain-terminal and an enhancement-gate-terminal, wherein the enhancement-source-terminal is coupled to the die-source-terminal, the enhancement-gate-terminal is coupled to the die-gate-terminal and the enhancement-drain-terminal is coupled to the depletion-source-terminal; and a clamp-circuit coupled between the depletion-source-terminal and the depletion-gate-terminal.
摘要翻译： 一种半导体器件，包括：芯片 - 源极端子，芯片 - 漏极端子和晶体管 - 栅极端子; 半导体芯片; 设置在所述半导体管芯上的绝缘栅极耗尽型晶体管，所述绝缘栅极耗尽型晶体管包括耗尽源极端子，耗尽 - 漏极端子和耗尽栅极端子，其中 耗尽漏极端子耦合到管芯漏极端子，耗尽栅极端子耦合到管芯源极端子; 增强型晶体管，其包括增强源极端子，增强型 - 漏极端子和增强型栅极端子，其中所述增强源极端子耦合到所述管芯源极端子，所述增强型 - 端子耦合到晶体管栅极端子，并且增强漏极端子耦合到耗尽源极端子; 以及耦合在耗尽源极端与耗尽栅极端子之间的钳位电路。
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公开(公告)号：US09472549B2
公开(公告)日：2016-10-18
申请号：US14056648
申请日：2013-10-17
申请人： NXP B.V.
发明人： Matthias Rose , Jan Sonsky , Philip Rutter
IPC分类号： H01H47/00 , H01L27/088 , H01L27/08 , H03K17/567 , H03K17/687 , H03K17/74
CPC分类号： H01L27/088 , H01L27/0814 , H03K17/567 , H03K17/6871 , H03K17/6874 , H03K17/74 , H03K2017/6875
摘要： A cascoded power semiconductor circuit has a clamp circuit between the source and gate of a gallium nitride or silicon carbide FET to provide avalanche protection for the cascode MOSFET transistor.
摘要翻译： 级联功率半导体电路在氮化镓或碳化硅FET的源极和栅极之间具有钳位电路，以提供共源共栅MOSFET晶体管的雪崩保护。
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公开(公告)号：US20210384825A1
公开(公告)日：2021-12-09
申请号：US17303127
申请日：2021-05-20
申请人： NXP B.V.
摘要： A burst-mode controller for a DC-DC converter includes an output module configured to provide a switch control signal to the DC-DC converter. The switch control signal includes a plurality of burst windows, each burst window corresponding to a period of a fixed-frequency burst clock and having a number of switching cycles. The burst-mode controller includes an on-time-control-module configured to receive a compensation signal based on the output voltage of the DC-DC converter and set an on-time of the switching cycles of the switch control signal based on the compensation signal. The burst-mode controller also includes a burst-control-module configured to regulate the on-time of the switching cycles of the switch control signal by setting the number of switching cycles for each burst window of the switch control signal.
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