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    APPARATUSES AND METHODS FOR DIRECT ACCESS HYBRID TESTING
    1.
    发明申请
    APPARATUSES AND METHODS FOR DIRECT ACCESS HYBRID TESTING 有权

    公开(公告)号：US20210104293A1

    公开(公告)日：2021-04-08

    申请号：US17124169

    申请日：2020-12-16

    申请人： MICRON TECHNOLOGY, INC.

    发明人： Chiaki Dono ,  Chikara Kondo ,  Roman A. Royer

    IPC分类号： G11C29/44 ,  G11C29/48 ,  G11C29/36 ,  G11C29/30

    摘要： Embodiments of the disclosure are drawn to apparatuses, systems, and methods for direct access hybrid testing. A memory device, such as a high bandwidth memory (HBM) may include direct access terminals. During a testing procedure, test instructions may be provided to the memory through the direct access terminals. The test instructions include a data pointer which is associated with one of a plurality of test patterns pre-loaded in the memory and an address. The selected test pattern may be written to, and subsequently read from, the memory cells associated with the address. The read test pattern may be compared to the selected test pattern to generate result information. The test patterns may be loaded to the memory, and the result information may be read out from the memory, in an operational mode different than the operational mode in which the test instructions are provided.

    APPARATUSES AND METHODS FOR SIGNAL ENCRYPTION IN HIGH BANDWIDTH MEMORY
    2.
    发明申请
    APPARATUSES AND METHODS FOR SIGNAL ENCRYPTION IN HIGH BANDWIDTH MEMORY 有权

    公开(公告)号：US20210097209A1

    公开(公告)日：2021-04-01

    申请号：US16589989

    申请日：2019-10-01

    申请人： MICRON TECHNOLOGY, INC.

    发明人： Chikara Kondo ,  Kazuhiro Kurihara

    IPC分类号： G06F21/85 ,  G06F21/79 ,  G06F21/60 ,  G06F12/14 ,  G11C29/12

    摘要： Embodiments of the disclosure are drawn to apparatuses, systems, and methods for signal encryption in high bandwidth memory. A high bandwidth memory (HBM) may include a mix of secure circuits and non-secure circuits, which are coupled to secure and non-secure registers respectively. Information may be communicated between the secure and non-secure registers along an interface. The information associated with the secure register may be encrypted. When information is written to the secure register, an encryption circuit in the HBM may first decrypt the information before it is written to the secure register. When information is read from the secure register, it may first be encrypted by the encryption circuit before it is provided along the interface.

    Multiple algorithmic pattern generator testing of a memory device
    3.
    发明授权
    Multiple algorithmic pattern generator testing of a memory device 有权

    公开(公告)号：US10937518B2

    公开(公告)日：2021-03-02

    申请号：US16218267

    申请日：2018-12-12

    申请人： MICRON TECHNOLOGY, INC.

    发明人： Roman A. Royer ,  Chikara Kondo ,  Chiaki Dono

    IPC分类号： G11C29/00 ,  G11C29/36 ,  G11C29/12 ,  G11C29/26 ,  G11C5/02 ,  G06F13/16 ,  G11C29/44 ,  G11C29/56

    摘要： Apparatuses including a test interface circuit that is configured to merge multiple independent traffic streams generated from individual algorithmic pattern generators (APGs) for communication with a memory device over a shared memory interface. The combination of multiple independent traffic streams, each with their own looping sequences and command timings, may generate a large set of random command sequences. The test interface circuit may include an arbiter circuit that merges a first independent traffic stream from a first APG and a second independent traffic stream from a second APG. Each of the first and second independent traffic streams are directed to different semi-independently-accessible portions of the memory device. The memory device may include a hybrid memory cube having independently accessible vaults or a high bandwidth memory device having independently accessible channels, in some examples. The test interface circuit may be included in a built-in self-test engine or in a standalone tester.

    SWITCHING REDUCTION BUS USING DATA BIT INVERSION WITH SHIELD LINES
    4.
    发明申请
    SWITCHING REDUCTION BUS USING DATA BIT INVERSION WITH SHIELD LINES 审中-公开

    公开(公告)号：US20190384739A1

    公开(公告)日：2019-12-19

    申请号：US16553552

    申请日：2019-08-28

    申请人： Micron Technology, Inc.

    发明人： Akinori Funahashi ,  Chikara Kondo

    IPC分类号： G06F13/42 ,  G06F13/16 ,  G11C5/06 ,  G11C8/18

    摘要： Apparatus and methods structured with respect to a data bus having a number of data lines and a number of shield lines can be implemented in a variety of applications. Such apparatus and methods can include driver and receiver circuits that operate to generate and/or decode a data bit inversion signal associated with data propagated on data lines of the data bus. The driver and receiver circuits may be arranged to operate on a two bit basis to interface with the data bus having data lines grouped with respect to the two bits with shield lines for the respective two bit data lines. Additional apparatus and methods are disclosed.

    System and method for write data bus control in a stacked memory device
    6.
    发明授权
    System and method for write data bus control in a stacked memory device 有权

    公开(公告)号：US10163469B2

    公开(公告)日：2018-12-25

    申请号：US15365563

    申请日：2016-11-30

    申请人： Micron Technology, Inc.

    发明人： Chikara Kondo ,  Tomoyuki Shibata ,  Chiaki Dono ,  Seiji Narui ,  Minehiko Uehara ,  Taihei Shido ,  Homare Sato

    IPC分类号： G11C7/10 ,  G11C19/28 ,  G11C7/22

    摘要： Apparatuses and methods for transmitting data between a plurality of chips are described. An example apparatus includes: a first chip, wherein the first chip includes a receiver that receives a data strobe signal and further generates an internal strobe signal responsive, at least in part, to the data strobe signal, the internal strobe signal including a first edge and a second edge following the first edge; a buffer circuit coupled to a set of input terminals and captures first data at the set of input terminals responsive, at least in part, to the first edge of the internal strobe signal and further captures second data at the set of input terminals responsive, at least in part, to the second edge of the internal strobe signal; a driver coupled between the buffer circuit and a set of data terminals and configured to be activated to provide the first and second data from the buffer circuit to the set of data terminals responsive, at least in part, to a control signal; and a width expanding circuit that provides the control signal responsive, at least in part, to the internal strobe signal.

    APPARATUSES AND METHODS FOR FIXING A LOGIC LEVEL OF AN INTERNAL SIGNAL LINE
    7.
    发明申请
    APPARATUSES AND METHODS FOR FIXING A LOGIC LEVEL OF AN INTERNAL SIGNAL LINE 有权
    用于固定内部信号线的逻辑电平的装置和方法

    公开(公告)号：US20160034340A1

    公开(公告)日：2016-02-04

    申请号：US14678375

    申请日：2015-04-03

    申请人： Micron Technology, Inc.

    发明人： CHIAKI DONO ,  Seiichi Maruno ,  Taihei Shido ,  Toshio Ninomiya ,  Chikara Kondo

    IPC分类号： G06F11/10

    CPC分类号： G06F11/1004 ,  G06F11/1016

    摘要： An apparatus includes a first external terminal, a first circuit, a signal line and a second circuit, The first external terminal receives at least one of data mask information and data bus inversion information. The first circuit performs one of an error check operation and as data bus invasion operation. The signal line is coupled between the first external terminal and the first circuit. The second circuit is coupled to the signal line and first a voltage level of the signal line at a substantially constant level responsive to a first control signal.

    摘要翻译： 一种装置包括第一外部终端，第一电路，信号线和第二电路。第一外部终端接收数据掩码信息和数据总线反转信息中的至少一个。 第一个电路执行错误检查操作和数据总线入侵操作之一。 信号线耦合在第一外部端子和第一电路之间。 第二电路耦合到信号线，并且首先响应于第一控制信号，以基本上恒定的电平将信号线的电压电平耦合。

    Shared error detection and correction memory
    10.
    发明授权
    Shared error detection and correction memory 有权

    公开(公告)号：US11222708B2

    公开(公告)日：2022-01-11

    申请号：US16537076

    申请日：2019-08-09

    申请人： Micron Technology, Inc.

    发明人： Tomoyuki Shibata ,  Chikara Kondo ,  Hiroyuki Tanaka

    IPC分类号： G11C29/38 ,  G11C29/12 ,  G11C29/00 ,  G11C29/14 ,  G11C29/36 ,  G11C29/42 ,  G11C29/44 ,  G11C29/48 ,  G11C5/02 ,  G11C29/04

    摘要： Apparatuses and methods of sharing error correction memory on an interface chip are described. An example apparatus includes: at least one memory chip having a plurality of first memory cells and an interface chip coupled to the at least one memory chip and having a control circuit and a storage area. The control circuit detects one or more defective memory cells of the first memory cells of the at least one memory chip. The control circuit further stores first defective address information of the one or more defective memory cells of the first memory cells into the storage area. The interface chip responds to the first defective address information and an access request to access the storage area in place of the at least one memory chip when the access request has been provided with respect to the one or more defective memory cells of the first memory cells.