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公开(公告)号：US09628035B2
公开(公告)日：2017-04-18
申请号：US14513387
申请日：2014-10-14
Applicant: MediaTek Inc.
Inventor： Hung-Chieh Tsai , Chi-Lun Lo , Chen-Yen Ho , Yu-Hsin Lin
CPC classification number: H03F3/45179 , H03F1/14 , H03F1/3211 , H03F1/483 , H03F3/193 , H03F3/3023 , H03F3/45 , H03F3/45076 , H03F3/45188 , H03F2200/36 , H03F2203/45222 , H03F2203/45521 , H03F2203/45526 , H03F2203/45626
Abstract: An implementation of an operational amplifier circuit includes a first stage amplifier circuit, a second stage amplifier circuit and a first feedforward circuit. The first stage amplifier circuit is coupled to a first input node for receiving a first input signal and amplifying the first input signal to generate a first amplified signal. The second stage amplifier circuit is coupled to the first stage amplifier circuit for receiving the first amplified signal and amplifying the first amplified signal to generate a first output signal at a first output node. The first feedforward circuit is coupled between the first input node and the second stage amplifier circuit for feeding the first input signal forward to the second stage amplifier circuit.
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公开(公告)号：US20210135673A1
公开(公告)日：2021-05-06
申请号：US17065526
申请日：2020-10-08
Applicant: MEDIATEK INC.
Inventor： Hung-Chieh Tsai , Sheng-Hui Liao
IPC: H03K19/0185 , G05F3/24
Abstract: The present invention provides a reference voltage buffer comprises a reference voltage generator, a first operational amplifier, a first transistor, a first group of resistors, a first load, a second transistor, a second group of resistors and a second load. In the reference voltage buffer, the first load and the second load use active device to increase the settling time, and the first load, the second load and the reference voltage generator of the reference voltage buffer are resigned to have the same characteristics in response to the temperature variation to overcome the PVT issue, and the first load and the second load of the reference voltage buffer use the open-loop design to have large full-scale of the output reference voltages.
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公开(公告)号：US10236851B2
公开(公告)日：2019-03-19
申请号：US15717966
申请日：2017-09-28
Applicant: MEDIATEK INC.
Inventor： Hung-Chieh Tsai
Abstract: A variable gain amplifier includes an input transistor, an auxiliary transistor, an active inductor and an input current replica circuit. The input transistor is arranged for receiving an input signal to generate an output signal at an output terminal. The auxiliary transistor is coupled to the output terminal of the input transistor, wherein a current of the output terminal flows into the input transistor and the auxiliary transistor. The active inductor is coupled to the output terminal of the input transistor. The input current replica circuit is coupled to the output terminal of the input transistor, wherein a current flowing through a portion of the input current replica circuit is equal to the current flowing through the input transistor, and both a current of the active inductor and the current of the portion of the input current replica circuit flow into the output terminal of the input transistor.
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公开(公告)号：US10187024B2
公开(公告)日：2019-01-22
申请号：US15488533
申请日：2017-04-17
Applicant: MEDIATEK INC.
Inventor： Hung-Chieh Tsai , Yu-Hsin Lin
Abstract: An amplifier includes an amplifying stage, a cascoded circuit, an input feed-forward circuit and an output stage. The amplifying stage is arranged receiving a differential input pair to generate an amplified differential input pair. The input feed-forward circuit is coupled to the cascoded circuit, and is arranged for feeding the differential input pair forward to the cascoded circuit. The output stage is coupled to the amplifying stage and the cascoded circuit, and is arranged for generating a differential output pair according to the amplified differential input pair and an output of the cascoded circuit.
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公开(公告)号：US09948318B1
公开(公告)日：2018-04-17
申请号：US15784198
申请日：2017-10-16
Applicant: MEDIATEK INC.
Inventor： Hung-Chieh Tsai
IPC: H03M3/00
Abstract: A delta-sigma modulator includes a receiving circuit, a loop filter, a quantizer with a negative capacitor circuit and a feedback circuit. The receiving circuit is arranged for receiving an input signal and a feedback signal to generate a first signal. The loop filter is coupled to the receiving circuit, and is arranged for receiving the first signal to generate a filtered signal. The quantizer is coupled to the loop filter, and is arranged for generating a digital output signal according to the filtered signal, wherein the negative capacitor circuit is arranged at an input terminal of the quantizer. The feedback circuit is arranged for receiving the digital output signal to generate the feedback signal.
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Patent Agency Ranking
公开(公告)号：US08952749B1
公开(公告)日：2015-02-10
申请号：US14038759
申请日：2013-09-27
Applicant: Mediatek Inc.
Inventor： Hung-Chieh Tsai , Chen-Yen Ho , Yu-Hsin Lin
CPC classification number: H03H11/1252 , H03H11/32
Abstract: A filter comprises an integrator, a signal feeding path, a first operational amplifier and a second capacitor. The integrator comprises a first input terminal and a first output terminal. The signal feeding path comprises: a first resistor, having a first terminal coupled to the first output terminal; a first capacitor, having a first terminal coupled to the second terminal of the first resistor; and a second resistor, having a first terminal coupled to the integrator and having a second terminal coupled to the second terminal of the first capacitor. The first operational amplifier comprises a second input terminal coupled to the second terminal of the first resistor and the first terminal of the first capacitor, and comprises a second output terminal. The second capacitor comprises a first terminal coupled to the second terminal of the first capacitor, and comprises a second terminal coupled to the second output terminal.
Abstract translation: 滤波器包括积分器，信号馈送路径，第一运算放大器和第二电容器。 积分器包括第一输入端和第一输出端。 信号馈送路径包括：第一电阻器，具有耦合到第一输出端子的第一端子; 第一电容器，具有耦合到第一电阻器的第二端子的第一端子; 以及第二电阻器，其具有耦合到积分器的第一端子，并具有耦合到第一电容器的第二端子的第二端子。 第一运算放大器包括耦合到第一电阻器的第二端子和第一电容器的第一端子的第二输入端子，并且包括第二输出端子。 第二电容器包括耦合到第一电容器的第二端子的第一端子，并且包括耦合到第二输出端子的第二端子。
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公开(公告)号：US09929742B2
公开(公告)日：2018-03-27
申请号：US15652207
申请日：2017-07-17
Applicant: MEDIATEK INC.
Inventor： Hung-Chieh Tsai
CPC classification number: H03M3/368 , H03F1/26 , H03F1/3223 , H03F1/3229 , H03F1/3247 , H03F3/45 , H03F3/45475 , H03F2200/411 , H03F2203/45116 , H03G3/20 , H03M3/422 , H03M3/436 , H03M3/458
Abstract: A circuit includes a first amplifying stage, a noise extraction circuit and a noise cancellation circuit. The first amplifying stage is arranged for receiving an input signal to generate an amplified input signal. The noise extraction circuit is coupled to the first amplifying stage, and is arranged for receiving at least the amplified input signal to generate a noise signal associated with noise components of the amplified input signal. The noise cancellation circuit is coupled to the first amplifying stage and the noise extraction circuit, and is arranged for cancelling noise components of the amplified input signal by using the noise signal generated by the noise extraction circuit, to generate a noise-cancelled amplified input signal.
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公开(公告)号：US09559674B2
公开(公告)日：2017-01-31
申请号：US15044114
申请日：2016-02-16
Applicant: MEDIATEK INC.
Inventor： Chen-Yen Ho , Yu-Hsin Lin , Hung-Chieh Tsai , Tze-Chien Wang
CPC classification number: H03K3/356113 , H03K3/356121 , H03K3/356191 , H03M1/066 , H03M1/0872 , H03M1/66 , H03M3/464
Abstract: A latch circuit includes an input stage, an amplifying stage and a clock gating circuit. The input stage is arranged for receiving at least a clock signal and a data control signal. The amplifying stage is coupled to the input stage and supplied by a supply voltage and a ground voltage, and is arranged for retaining a data value and outputting the data value according to the clock signal and the data control signal. The clock gating circuit is coupled to the amplifying stage, and is arranged for avoiding a short-circuit current between the supply voltage and the ground voltage.
Abstract translation: 锁存电路包括输入级，放大级和时钟门控电路。 输入级被布置成用于接收至少一个时钟信号和数据控制信号。 放大级与输入级耦合，由供电电压和接地电压提供，并被配置为保持数据值并根据时钟信号和数据控制信号输出数据值。 时钟门控电路耦合到放大级，并且被布置为避免电源电压和接地电压之间的短路电流。
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公开(公告)号：US09154083B2
公开(公告)日：2015-10-06
申请号：US14643240
申请日：2015-03-10
Applicant: MediaTek Inc.
Inventor： Chen-Yen Ho , Chi-Lun Lo , Hung-Chieh Tsai , Yu-Hsin Lin
CPC classification number: H03F1/0205 , H03F3/265 , H03F3/30 , H03F3/3023 , H03F3/45071 , H03F3/45179 , H03F3/45183 , H03F3/45475 , H03F2200/18 , H03F2203/30021 , H03F2203/30033 , H03F2203/45022 , H03F2203/45134 , H03F2203/45138 , H03M3/39 , H03M3/50
Abstract: An amplifier includes a front-end gain stage and an AC-coupled push-pull output stage. The AC-coupled push-pull output stage includes a first transistor, having a source, a drain and a gate, wherein the source of the first transistor is coupled to a first voltage level. The AC-coupled push-pull output stage further includes a second transistor, having a source, a drain and a gate, wherein the source of the second transistor is coupled to a second voltage level, the gate of the second transistor is coupled to the front-end gain stage, and the drain of the second transistor is coupled to the drain of the first transistor to form an output terminal of the amplifier. Further, the AC-coupled push-pull output stage includes an AC-coupled capacitor, which is a passive two terminal electrical component coupled between the front-end gain stage and the gate of the first transistor.
Abstract translation: 放大器包括前端增益级和AC耦合推挽输出级。 AC耦合推挽输出级包括具有源极，漏极和栅极的第一晶体管，其中第一晶体管的源极耦合到第一电压电平。 AC耦合推挽输出级还包括具有源极，漏极和栅极的第二晶体管，其中第二晶体管的源极耦合到第二电压电平，第二晶体管的栅极耦合到 前端增益级，第二晶体管的漏极耦合到第一晶体管的漏极，以形成放大器的输出端。 此外，AC耦合推挽输出级包括AC耦合电容器，其是耦合在前端增益级与第一晶体管的栅极之间的无源双端电气部件。
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公开(公告)号：US09019136B2
公开(公告)日：2015-04-28
申请号：US14097451
申请日：2013-12-05
Applicant: MediaTek Inc.
Inventor： Chen-Yen Ho , Hung-Chieh Tsai , Yu-Hsin Lin
Abstract: A sigma-delta modulator is provided for generating a digital output signal. The sigma-delta modulator is used to generate a digital output signal. The sigma-delta modulator includes a multi-stage loop filter and a quantizer. The multi-stage loop filter receives an analog input signal and generates an integrated output signal according to the analog input signal. The quantizer is coupled to the multi-stage loop filter. The quantizer receives the integrated output signal and quantizes the integrated output signal to generate the digital output signal. Different feed-forward paths of the sigma-delta modulator are available for different frequency bands.
Abstract translation: 提供Σ-Δ调制器用于产生数字输出信号。 Σ-Δ调制器用于产生数字输出信号。 Σ-Δ调制器包括多级环路滤波器和量化器。 多级环路滤波器接收模拟输入信号，并根据模拟输入信号产生积分输出信号。 量化器耦合到多级环路滤波器。 量化器接收积分输出信号并量化积分输出信号以产生数字输出信号。 Σ-Δ调制器的不同前馈路径可用于不同的频带。
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