公开(公告)号：US4899066A

公开(公告)日：1990-02-06

申请号：US848563

申请日：1986-04-07

Applicant: Masatoshi Aikawa ,  Hiromasa Nakagawa ,  Tsunenori Umeki

Inventor： Masatoshi Aikawa ,  Hiromasa Nakagawa ,  Tsunenori Umeki

IPC: G11C17/18 ,  G11C8/10 ,  G11C16/06 ,  G11C17/00 ,  H03K19/096

CPC classification number: G11C8/10 ,  H03K19/0963

Abstract: A complementary metal oxide semiconductor logic circuit comprises a signal line OR-connecting a plurality of MOS transistors which are turned on/off by a plurality of decoder outputs. The signal line is divided by a MOS-FET in two portions including a portion on an output side provided with an inverter and an OR-connected transistors side, so that respective portions of the signal line as divided are precharged by separate precharging MOS transistors.

Abstract translation: 互补金属氧化物半导体逻辑电路包括通过多个解码器输出导通/断开的多个MOS晶体管OR连接的信号线。 信号线由MOS-FET分为两部分，包括设置有反相器的输出侧的一部分和与OR连接的晶体管侧，使得分开的信号线的各个部分由分开的预充电MOS晶体管预充电。

公开(公告)号：US4952522A

公开(公告)日：1990-08-28

申请号：US213102

申请日：1988-06-28

Applicant: Akira Yamada ,  Tsunenori Umeki ,  Masatoshi Aikawa

Inventor： Akira Yamada ,  Tsunenori Umeki ,  Masatoshi Aikawa

IPC: H01L21/027 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/8238 ,  H01L21/0274 ,  H01L27/0921

Abstract: A novel method for making complementary semiconductor IC devices is described. The method includes the steps of: preparing a N-type semiconductor substrate; preparing a first mask for forming a P-well in the N-type substrate; forming the P-well in the N-type substrate using the first mask; preparing a second mask for forming a first P-type diffusion regions in the substrate and in the P-well; preparing a third mask for forming N-type diffusion regions in the substrate and in the P-well; preparing a fourth mask for forming a second P-type diffusion regions in the unoccupied areas of the N-type substrate and the P-well by carrying out reversing, AND and OR processing of the first, second and third masks, and forming the P-type diffusion regions in the prescribed areas of the substrate and the P-well by placing the fourth mask on the substrate.

Abstract translation: 描述了制造互补半导体IC器件的新颖方法。 该方法包括以下步骤：制备N型半导体衬底; 制备用于在N型衬底中形成P阱的第一掩模; 使用第一掩模在N型衬底中形成P阱; 制备用于在衬底和P阱中形成第一P型扩散区的第二掩模; 制备用于在衬底和P阱中形成N型扩散区的第三掩模; 制备用于在N型衬底和P阱的未占用区域中形成第二P型扩散区的第四掩模，通过执行第一，第二和第三掩模的反转，AND和OR处理，并形成P 通过将第四掩模放置在基板上而在基板的规定区域中形成P型扩散区域。

公开(公告)号：US5454088A

公开(公告)日：1995-09-26

申请号：US62183

申请日：1993-05-17

Applicant: Hiromasa Nakagawa ,  Tsunenori Umeki

Inventor： Hiromasa Nakagawa ,  Tsunenori Umeki

IPC: G06F9/26

CPC classification number: G06F9/264

Abstract: A microprogram control device controls a data path section provided in a CPU, which uses a microcode stored in a microprogram memory by using a microprogramming method. The control device includes an instruction register for storing an instruction code which is received from a data bus and an address generator for generating an address signal to access the microprogram memory, from the output of the instruction register. The address generator uses a first address decoder for decoding the type of the instruction from a particular bit in the instruction code and a second address decoder for decoding the addressing mode of the instruction from another particular bit of the instruction code. A third address decoder is included for designating the timing for accessing the microprogram memory at each cycle of the instruction.

Abstract translation: 微程序控制装置通过使用微程序方法来控制CPU中提供的数据路径部分，其使用存储在微程序存储器中的微代码。 控制装置包括指令寄存器，用于从指令寄存器的输出存储从数据总线接收的指令代码和用于产生访问微程序存储器的地址信号的地址生成器。 地址生成器使用第一地址解码器来对来自指令代码中的特定位的指令的类型进行解码，以及第二地址解码器，用于从指令代码的另一特定位解码指令的寻址模式。 包括第三地址解码器，用于指定在指令的每个周期访问微程序存储器的定时。

公开(公告)号：US5423052A

公开(公告)日：1995-06-06

申请号：US21431

申请日：1993-02-23

Applicant: Kenji Oonishi ,  Tsunenori Umeki

Inventor： Kenji Oonishi ,  Tsunenori Umeki

IPC: G06F7/38 ,  G06F7/508 ,  G06F7/57 ,  G06F9/305 ,  G06F9/00 ,  G06F9/302

CPC classification number: G06F7/57

Abstract: For obtaining a central processing unit to perform, with the same operation code, an operation in which a carry input is effective and an operation in which the carry input is invalid or an operation in which a borrow input is effective and an operation in which the borrow input is invalid, between an output of a carry and borrow flag and a carry and borrow input of an ALU there is provided a switching circuit to switch the input of the ALU by a control signal different from a control signal of the central processing unit due to an operation code.

Abstract translation: 为了获得中央处理单元，以相同的操作代码执行进位输入有效的操作和进位输入无效的操作或者借用输入有效的操作，以及操作 借位输入无效，在进位和借位标志的输出与ALU的进位和借位输入之间提供切换电路，以通过与中央处理单元的控制信号不同的控制信号切换ALU的输入 由于操作代码。

公开(公告)号：US5014105A

公开(公告)日：1991-05-07

申请号：US529762

申请日：1990-05-31

Applicant: Masayuki Hata ,  Tsunenori Umeki

Inventor： Masayuki Hata ,  Tsunenori Umeki

IPC: H01L27/08 ,  H01L27/092

CPC classification number: H01L27/0921

Abstract: A complementary IC device comprises: an n-semiconductor substrate; a p-well formed within the n-substrate: a n-channel FET (field effect transistor) formed on the p-well, the n-channel FET including an n-source connected to a first grounded line and an n-drain connected to an output line; a p-channel FET formed on the n-substrate, the p-channel FET including a p-source connected to a first voltage source line and a p-drain connected to the output line; a contact p-region formed on the p-well for providing electrical connection between the p-well and a second grounded line; and a contact n-region formed on the n-substrate for providing electrical connection between the n-substrate and a second voltage source line.

Abstract translation: 互补IC器件包括：n半导体衬底; 形成在n衬底内的p阱：形成在p阱上的n沟道FET（场效应晶体管），n沟道FET包括连接到第一接地线的n源极和连接到n阱的n沟道 到输出线; 形成在所述n衬底上的p沟道FET，所述p沟道FET包括连接到第一电压源线的p源和连接到所述输出线的p型漏极; 形成在p阱上的用于在p阱和第二接地线之间提供电连接的接触p区; 以及形成在n衬底上的接触n区，用于提供n衬底和第二电压源线之间的电连接。

公开(公告)号：US4868627A

公开(公告)日：1989-09-19

申请号：US213105

申请日：1988-06-28

Applicant: Akira Yamada ,  Tsunenori Umeki

Inventor： Akira Yamada ,  Tsunenori Umeki

IPC: H01L21/8238 ,  H01L27/092 ,  H03K19/003

CPC classification number: H03K19/00361 ,  H01L27/092

Abstract: A complementary semiconductor integrated circuit for absorbing a noise comprises an n-type semiconductor substrate maintained at a supply voltage, a p-type well maintained at the reference voltage potential, an n-type region formed in the n-type semiconductor substrate and connected to the supply voltage, a polysilicon layer formed on the n-type region through an insulating film and connected to the reference voltage, whereby a capacitance is formed by the n-type region and the polysilicon layer formed on the n-type region through the insulating film. A noise included in the supply voltage is absorbed by the capacitance.

Abstract translation: 用于吸收噪声的互补半导体集成电路包括保持在电源电压的n型半导体衬底，保持在参考电压电位的p型阱，形成在n型半导体衬底中的n型区域，并连接到 电源电压，通过绝缘膜形成在n型区域上并连接到参考电压的多晶硅层，由此通过绝缘体在n型区域上形成的n型区域和多晶硅层形成电容 电影。 包括在电源电压中的噪声被电容吸收。

公开(公告)号：US4639892A

公开(公告)日：1987-01-27

申请号：US556387

申请日：1983-11-30

Applicant: Shigeo Mizugaki ,  Tsunenori Umeki

Inventor： Shigeo Mizugaki ,  Tsunenori Umeki

IPC: G11C17/00 ,  G11C17/12 ,  G11C17/16 ,  H01L21/8246 ,  H01L27/112 ,  H01L29/78 ,  G11C11/40

CPC classification number: G11C17/16

Abstract: A semiconductor read-only memory device includes first and second MOS field effect mode transistors (MOSFET) as memory elements storing either one of binary values of binary information. The first MOSFET has such a relatively long effective gate length that it becomes conductive upon receipt of a first relatively high gate voltage applied thereto as a memory selection signal and becomes non-conductive upon receipt of a second relatively low gate voltage. The second MOSFET, on the other hand, has such a relatively short effective gate length that it becomes conductive whether the first or second gate voltage is applied thereto.

Abstract translation: 半导体只读存储器件包括作为存储二进制信息的二进制值之一的存储器元件的第一和第二MOS场效应晶体管（MOSFET）。 第一MOSFET具有这样相当长的有效栅极长度，其在接收到施加到其上的第一相对高的栅极电压时变为导通，作为存储器选择信号，并且在接收到第二相对低的栅极电压时变得不导通。 另一方面，第二MOSFET具有这样的相对较短的有效栅极长度，无论其施加第一或第二栅极电压，其都变得导通。

公开(公告)号：US5928354A

公开(公告)日：1999-07-27

申请号：US357551

申请日：1994-12-16

Applicant: Tsunenori Umeki ,  Hirohiko Inoue

Inventor： Tsunenori Umeki ,  Hirohiko Inoue

IPC: G06F9/32 ,  G06F9/38 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06

CPC classification number: G06F9/3802 ,  G06F9/3814

Abstract: A memory access method in a microcomputer for a CPU to fetch an instruction code from a memory when an instruction queue buffer does not contain the instruction code, comprising the steps of fetching the instruction code from a high-speed memory directly to the CPU, if the instruction code is in the high speed memory, or fetching the instruction code from a low-speed memory to the instruction queue buffer, if the instruction code is in the low-speed memory, then fetching the instruction code from the instruction queue buffer to the CPU.

Abstract translation: 一种用于CPU的微型计算机中的存储器访问方法，用于当指令队列缓冲器不包含指令代码时，从存储器取出指令代码，包括以下步骤：将指令代码从高速存储器直接提取到CPU，如果 如果指令代码在低速存储器中，则指令代码在高速存储器中，或者将指令代码从低速存储器提取到指令队列缓冲器，然后从指令队列缓冲器中取出指令代码 CPU。

公开(公告)号：US5349666A

公开(公告)日：1994-09-20

申请号：US838633

申请日：1992-02-20

Applicant: Mitsuru Adachi ,  Tsunenori Umeki

Inventor： Mitsuru Adachi ,  Tsunenori Umeki

IPC: G06F13/00 ,  G06F1/26 ,  G06F3/00 ,  G06F15/78 ,  G08B21/00 ,  H03H11/00 ,  H03K5/08

CPC classification number: G06F1/26

Abstract: A microcomputer that reduces through current of output buffers, and thus, reduces power line fluctuation that occurs when a large number of the bus lines connected to output buffers change state at the same time. The through current (or punch-through current) is reduced through the use of a detector circuit that detects the number of bus lines which are changing state and a decoder circuit that changes the impedance of output buffers, which drive the bus lines to external components, when the number of bus lines changing state at a given time exceeds a predetermined number.

Abstract translation: 减少输出缓冲器电流的微型计算机，从而减少了当连接到输出缓冲器的大量总线线路同时改变状态时发生的电力线波动。 通过使用检测正在改变状态的总线线路的检测器电路来减少直流电流（或穿通电流），以及改变输出缓冲器的阻抗的解码器电路，其将总线驱动到外部部件 当在给定时间改变状态的总线数量超过预定数量时。

公开(公告)号：US5204842A

公开(公告)日：1993-04-20

申请号：US563875

申请日：1990-08-07

Applicant: Tsunenori Umeki

Inventor： Tsunenori Umeki

IPC: G11C8/12 ,  G11C17/12 ,  H01L27/112

CPC classification number: H01L27/112 ,  G11C17/12 ,  G11C8/12

Abstract: An AND type read-only memory (D-A-ROM), includes a memory unit divided into blocks in a row direction and into sub-blocks a column direction, a Y decoder, an X decoder and a column selector. An output of the Y decoder and an output of the X decoder are connected to the memory blocks by first and second gate electrode connectors, respectively. A read control signal from the CPU is connected to each of the memory blocks by third gate electrode connectors. In addition, the output of the X decoder is supplied in parallel to each of the memory sub-blocks through bypass connectors including aluminum interconnections of a separately formed second layer. The read control signal is supplied in parallel to each of the memory sub-blocks through bypass interconnections of the second layer.

Abstract translation: AND型只读存储器（D-A-ROM）包括被划分为行方向的块和存储列方向的子块的存储器单元，Y解码器，X解码器和列选择器。 Y解码器的输出和X解码器的输出分别通过第一和第二栅电极连接器连接到存储器块。 来自CPU的读取控制信号通过第三栅电极连接器连接到每个存储块。 此外，X解码器的输出通过包括单独形成的第二层的铝互连的旁路连接器并行提供给每个存储子块。 读取控制信号通过第二层的旁路互连并行地提供给每个存储器子块。