公开(公告)号：US5535359A

公开(公告)日：1996-07-09

申请号：US387980

申请日：1995-02-13

Applicant: Masayuki Hata ,  Hiromasa Nakagawa ,  Tatsuo Yamada

Inventor： Masayuki Hata ,  Hiromasa Nakagawa ,  Tatsuo Yamada

IPC: G06F12/08

CPC classification number: G06F12/0864 ,  G06F12/0848 ,  G06F12/0888

Abstract: A computer system is provided with a plurality of cache memories. Each cache memory stores data corresponding to part of main memory address space without overlapping with each other, thereby enabling capacity of the cache memory to be increased with ease. An address mask register is used to allocate the portion of main memory address space stored in each cache.

Abstract translation: 计算机系统设置有多个高速缓存存储器。 每个高速缓冲存储器存储与主存储器地址空间的一部分相对应的数据，而不会彼此重叠，从而容易地增加高速缓冲存储器的容量。 地址掩码寄存器用于分配存储在每个高速缓存中的主存储器地址空间的一部分。

公开(公告)号：US5459852A

公开(公告)日：1995-10-17

申请号：US377300

申请日：1995-01-23

Applicant: Hiromasa Nakagawa ,  Akira Yamada ,  Masayuki Hata

Inventor： Hiromasa Nakagawa ,  Akira Yamada ,  Masayuki Hata

IPC: G06F12/08 ,  G06F12/12 ,  G06F12/06

CPC classification number: G06F12/0879 ,  G06F12/0859

Abstract: A data processor which accesses a memory system only by a block transfer mode for transferring multiple data from the memory system when a cache misses a CPU read-access request for a single data. The data of the address designated by the CPU is read simultaneously into the CPU and cache in parallel from the memory system. After the CPU completes this read-access, the cache is then adapted to continue to read the rest of the multiple data transferred in the block transfer mode. During this time, the CPU does not newly assert an address signal, a bus control signal, and the like but continues to execute its internal processing, such as pipeline processing.

Abstract translation: 一种数据处理器，仅当通过块传送模式访问存储器系统，以便在高速缓存未命中单个数据的CPU读取访问请求时从存储器系统传送多个数据。 由CPU指定的地址的数据从存储器系统并行读取到CPU中并缓存。 在CPU完成该读取访问之后，高速缓存然后适于继续读取以块传送模式传送的多个数据的其余部分。 在此期间，CPU不会新建地址信号，总线控制信号等，而是继续执行其内部处理，例如流水线处理。

公开(公告)号：US4899066A

公开(公告)日：1990-02-06

申请号：US848563

申请日：1986-04-07

Applicant: Masatoshi Aikawa ,  Hiromasa Nakagawa ,  Tsunenori Umeki

Inventor： Masatoshi Aikawa ,  Hiromasa Nakagawa ,  Tsunenori Umeki

IPC: G11C17/18 ,  G11C8/10 ,  G11C16/06 ,  G11C17/00 ,  H03K19/096

CPC classification number: G11C8/10 ,  H03K19/0963

Abstract: A complementary metal oxide semiconductor logic circuit comprises a signal line OR-connecting a plurality of MOS transistors which are turned on/off by a plurality of decoder outputs. The signal line is divided by a MOS-FET in two portions including a portion on an output side provided with an inverter and an OR-connected transistors side, so that respective portions of the signal line as divided are precharged by separate precharging MOS transistors.

Abstract translation: 互补金属氧化物半导体逻辑电路包括通过多个解码器输出导通/断开的多个MOS晶体管OR连接的信号线。 信号线由MOS-FET分为两部分，包括设置有反相器的输出侧的一部分和与OR连接的晶体管侧，使得分开的信号线的各个部分由分开的预充电MOS晶体管预充电。

公开(公告)号：US4908690A

公开(公告)日：1990-03-13

申请号：US106880

申请日：1987-10-13

Applicant: Masayuki Hata ,  Hiromasa Nakagawa

Inventor： Masayuki Hata ,  Hiromasa Nakagawa

IPC: H01L21/3205 ,  H01L21/822 ,  H01L23/52 ,  H01L23/522 ,  H01L23/528 ,  H01L27/04

CPC classification number: H01L23/522 ,  H01L23/528 ,  H01L2924/0002

Abstract: A semiconductor integrated circuit device includes a semiconductor substrate and a wiring layer formed on the substrate. An output buffer transistor is provided with its gate formed along the direction of the wiring. The resulting device has improved area efficiency and is less susceptible to wiring element slide without requiring slits to be formed in the wiring structure--and thus also has lower current density.

Abstract translation: 半导体集成电路器件包括半导体衬底和形成在衬底上的布线层。 输出缓冲晶体管设置有沿着布线方向形成的栅极。 所得到的器件具有改善的面积效率，并且不易于布线元件滑动，而不需要在布线结构中形成狭缝，并且因此也具有较低的电流密度。

公开(公告)号：US5544341A

公开(公告)日：1996-08-06

申请号：US454893

申请日：1995-05-31

Applicant: Hiromasa Nakagawa ,  Akira Yamada ,  Masayuki Hata

Inventor： Hiromasa Nakagawa ,  Akira Yamada ,  Masayuki Hata

IPC: G06F12/08 ,  G11C29/00 ,  G06F13/00 ,  G06F11/00

CPC classification number: G11C29/88 ,  G06F12/0879

Abstract: A data processor and method for preventing access to a cache memory when an abnormality occurs during a block data transfer. The data processor is provided with a central processing unit (CPU), a memory and the cache which stores a part of the data being stored in the memory. When the data to be accessed by the central processing unit is not stored in the cache, the data processor employs a block transfer method where the central processing unit reads out from the memory a block of data, including a predetermined number of data (words) in which the data to be accessed is located. When an abnormality, such as a parity error, is detected in transferring a data word in the block of data to be accessed, the cache is inhibited from reading another data word in the block to be accessed, and the CPU stops reading out the rest of the block of data to be read out from the memory, so that the central processing unit can immediately take action to respond to the abnormality.

Abstract translation: 一种用于在块数据传送期间发生异常时防止对高速缓存存储器的访问的数据处理器和方法。 数据处理器设置有中央处理单元（CPU），存储器和存储存储在存储器中的一部分数据的高速缓存。 当中央处理单元要访问的数据不存储在高速缓存中时，数据处理器采用块传送方法，其中中央处理单元从存储器读出包括预定数量的数据（字）的数据块， 其中要访问的数据位于其中。 当在传送要访问的数据块中的数据字中检测到诸如奇偶校验错误的异常时，禁止高速缓存读取要访问的块中的另一个数据字，并且CPU停止读出其余部分 的数据块从存储器读出，使得中央处理单元可以立即采取动作来响应异常。

公开(公告)号：US5454088A

公开(公告)日：1995-09-26

申请号：US62183

申请日：1993-05-17

Applicant: Hiromasa Nakagawa ,  Tsunenori Umeki

Inventor： Hiromasa Nakagawa ,  Tsunenori Umeki

IPC: G06F9/26

CPC classification number: G06F9/264

Abstract: A microprogram control device controls a data path section provided in a CPU, which uses a microcode stored in a microprogram memory by using a microprogramming method. The control device includes an instruction register for storing an instruction code which is received from a data bus and an address generator for generating an address signal to access the microprogram memory, from the output of the instruction register. The address generator uses a first address decoder for decoding the type of the instruction from a particular bit in the instruction code and a second address decoder for decoding the addressing mode of the instruction from another particular bit of the instruction code. A third address decoder is included for designating the timing for accessing the microprogram memory at each cycle of the instruction.

Abstract translation: 微程序控制装置通过使用微程序方法来控制CPU中提供的数据路径部分，其使用存储在微程序存储器中的微代码。 控制装置包括指令寄存器，用于从指令寄存器的输出存储从数据总线接收的指令代码和用于产生访问微程序存储器的地址信号的地址生成器。 地址生成器使用第一地址解码器来对来自指令代码中的特定位的指令的类型进行解码，以及第二地址解码器，用于从指令代码的另一特定位解码指令的寻址模式。 包括第三地址解码器，用于指定在指令的每个周期访问微程序存储器的定时。

公开(公告)号：US5638537A

公开(公告)日：1997-06-10

申请号：US690401

申请日：1996-07-25

Applicant: Akira Yamada ,  Masayuki Hata ,  Hiromasa Nakagawa ,  Koichi Nishida

Inventor： Akira Yamada ,  Masayuki Hata ,  Hiromasa Nakagawa ,  Koichi Nishida

IPC: G06F12/08 ,  G06F113/16

CPC classification number: G06F12/0848 ,  G06F12/0888

Abstract: A cache memory operates in a first mode, in which a cache hit occurs, and in a second mode, in which a cache miss occurs. A data processor operates in a first state in which instructions are accessed from memory and in a second state in which data is accessed from memory. Cache memory has a condition setting circuit which distinguishes instruction caching from a data caching. The processor sends an access-type signal which is compared with the access-type set in the condition setting circuit. When the access-type signal does not coincide with the contents of the condition setting circuit, a third state is declared which links the main memory and cache memory.

Abstract translation: 高速缓冲存储器在发生高速缓存命中的第一模式中运行，并且在发生高速缓存未命中的第二模式中操作。 数据处理器在其中从存储器访问指令的第一状态和从存储器访问数据的第二状态中操作。 缓存存储器具有将指令缓存与数据高速缓存区分开的条件设置电路。 处理器发送与条件设置电路中设置的访问类型进行比较的访问类型信号。 当访问类型信号与条件设置电路的内容不一致时，声明连接主存储器和高速缓冲存储器的第三状态。

公开(公告)号：US4807176A

公开(公告)日：1989-02-21

申请号：US838302

申请日：1986-03-10

Applicant: Akira Yamada ,  Toyohiko Yoshida ,  Hiromasa Nakagawa

Inventor： Akira Yamada ,  Toyohiko Yoshida ,  Hiromasa Nakagawa

IPC: G06F7/50 ,  G06F7/503 ,  G06F7/506

CPC classification number: G06F7/503 ,  G06F2207/3872

Abstract: A Manchester type carry propagation circuit of this invention has a precharge clock signal (24) applied to the gate of an NMOS transistor (23) having a high threshold, to precharge a carry signal line (22) to an intermediate potential. When a carry signal (27) of the preceding stage attains to the "H" level, a transistor (26) turns on to transmit the potential of the carry signal line (22) to the succeeding stage, and when a carry propagation signal (37) attains to the "H" level, a transistor (36) turns on to propagate a carry of the preceding stage to the carry signal line (22). Then, the intermediate level of the carry signal line (22) is pulled up to the level of the source potential (21) by a pull-up circuit (30). Consequently, the level of the carry signal line (22) can be propagated to the succeeding stage at high speed.

Abstract translation: 本发明的曼彻斯特式进位传播电路具有预加电时钟信号（24），该预充电时钟信号（24）施加到具有高阈值的NMOS晶体管（23）的栅极，以将进位信号线（22）预充电至中间电位。 当前级的进位信号（27）达到“H”电平时，晶体管（26）导通，将进位信号线（22）的电位传输到后级，当进位传播信号 37）达到“H”电平，晶体管（36）导通，将前级的进位传送到进位信号线（22）。 然后，通过上拉电路（30）将进位信号线（22）的中间电平上拉到电位电平（21）的电平。 因此，进位信号线（22）的电平可以高速传播到后级。