公开(公告)号：US4807176A

公开(公告)日：1989-02-21

申请号：US838302

申请日：1986-03-10

Applicant: Akira Yamada ,  Toyohiko Yoshida ,  Hiromasa Nakagawa

Inventor： Akira Yamada ,  Toyohiko Yoshida ,  Hiromasa Nakagawa

IPC: G06F7/50 ,  G06F7/503 ,  G06F7/506

CPC classification number: G06F7/503 ,  G06F2207/3872

Abstract: A Manchester type carry propagation circuit of this invention has a precharge clock signal (24) applied to the gate of an NMOS transistor (23) having a high threshold, to precharge a carry signal line (22) to an intermediate potential. When a carry signal (27) of the preceding stage attains to the "H" level, a transistor (26) turns on to transmit the potential of the carry signal line (22) to the succeeding stage, and when a carry propagation signal (37) attains to the "H" level, a transistor (36) turns on to propagate a carry of the preceding stage to the carry signal line (22). Then, the intermediate level of the carry signal line (22) is pulled up to the level of the source potential (21) by a pull-up circuit (30). Consequently, the level of the carry signal line (22) can be propagated to the succeeding stage at high speed.

Abstract translation: 本发明的曼彻斯特式进位传播电路具有预加电时钟信号（24），该预充电时钟信号（24）施加到具有高阈值的NMOS晶体管（23）的栅极，以将进位信号线（22）预充电至中间电位。 当前级的进位信号（27）达到“H”电平时，晶体管（26）导通，将进位信号线（22）的电位传输到后级，当进位传播信号 37）达到“H”电平，晶体管（36）导通，将前级的进位传送到进位信号线（22）。 然后，通过上拉电路（30）将进位信号线（22）的中间电平上拉到电位电平（21）的电平。 因此，进位信号线（22）的电平可以高速传播到后级。

公开(公告)号：US07346760B2

公开(公告)日：2008-03-18

申请号：US09855594

申请日：2001-05-16

Applicant: Toyohiko Yoshida ,  Akira Yamada ,  Hisakazu Sato

Inventor： Toyohiko Yoshida ,  Akira Yamada ,  Hisakazu Sato

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3814 ,  G06F7/5443 ,  G06F9/3802 ,  G06F9/381 ,  G06F9/3822 ,  G06F9/3875

Abstract: When fetching an instruction from a plurality of memory banks, a first pipeline cycle corresponding to selection of a memory bank and a second pipeline cycle corresponding to instruction readout are generated to carry out a pipeline process. Only the selected memory bank can be precharged to allow reduction of power consumption. Since the first and second pipeline cycles are effected in parallel, the throughput of the instruction memory can be improved.

Abstract translation: 当从多个存储体获取指令时，生成对应于存储器组的选择的第一流水线循环和对应于指令读出的第二流水线循环，以执行流水线处理。 只有选定的存储体可以被预先充电，以减少功耗。 由于第一和第二流水线周期是并行实现的，因此可以提高指令存储器的吞吐量。

公开(公告)号：US07694109B2

公开(公告)日：2010-04-06

申请号：US11987704

申请日：2007-12-04

Applicant: Toyohiko Yoshida ,  Akira Yamada ,  Hisakazu Sato

Inventor： Toyohiko Yoshida ,  Akira Yamada ,  Hisakazu Sato

IPC: G06F12/06

CPC classification number: G06F9/3814 ,  G06F7/5443 ,  G06F9/3802 ,  G06F9/381 ,  G06F9/3822 ,  G06F9/3875

Abstract: When fetching an instruction from a plurality of memory banks, a first pipeline cycle corresponding to selection of a memory bank and a second pipeline cycle corresponding to instruction readout are generated to carry out a pipeline process. Only the selected memory bank can be precharged to allow reduction of power consumption. Since the first and second pipeline cycles are effected in parallel, the throughput of the instruction memory can be improved.

Abstract translation: 当从多个存储体获取指令时，生成对应于存储器组的选择的第一流水线循环和对应于指令读出的第二流水线循环，以执行流水线处理。 只有选定的存储体可以被预先充电，以减少功耗。 由于第一和第二流水线周期是并行实现的，因此可以提高指令存储器的吞吐量。

公开(公告)号：US20080133887A1

公开(公告)日：2008-06-05

申请号：US11987704

申请日：2007-12-04

Applicant: Toyohiko Yoshida ,  Akira Yamada ,  Hisakazu Sato

Inventor： Toyohiko Yoshida ,  Akira Yamada ,  Hisakazu Sato

IPC: G06F9/38

CPC classification number: G06F9/3814 ,  G06F7/5443 ,  G06F9/3802 ,  G06F9/381 ,  G06F9/3822 ,  G06F9/3875

Abstract: When fetching an instruction from a plurality of memory banks, a first pipeline cycle corresponding to selection of a memory bank and a second pipeline cycle corresponding to instruction readout are generated to carry out a pipeline process. Only the selected memory bank can be precharged to allow reduction of power consumption. Since the first and second pipeline cycles are effected in parallel, the throughput of the instruction memory can be improved.

公开(公告)号：US06016543A

公开(公告)日：2000-01-18

申请号：US942295

申请日：1997-10-01

Applicant: Kazumasa Suzuki ,  Atsushi Mohri ,  Akira Yamada ,  Toyohiko Yoshida

Inventor： Kazumasa Suzuki ,  Atsushi Mohri ,  Akira Yamada ,  Toyohiko Yoshida

IPC: G06F9/38 ,  G06F11/14

CPC classification number: G06F9/30167 ,  G06F9/30072 ,  G06F9/3826 ,  G06F9/3842 ,  G06F9/3885

Abstract: In a microprocessor having conditional execution instructions, an execution halt circuit incorporated in an instruction decoder temporarily halts the execution of a current instruction according to the operation result of a preceding instruction in a program. When a conditional execution decision circuit judges to cancel the execution of the preceding instruction, the conditional execution decision circuit cancels a start signal indicating to initiate the operation of the preceding instruction. Furthermore, the conditional execution decision section or circuit judges whether a conditional data stored in a general purpose flag is equal to a condition stored in an execution conditional field, and bypass control sections control use of bypasses and data passes for data transfer operation according to the decision result of the conditional execution decision section.

Abstract translation: 在具有条件执行指令的微处理器中，结合在指令解码器中的执行停止电路根据程序中的前一指令的操作结果临时停止当前指令的执行。 当条件执行判定电路判断取消前一指令的执行时，条件执行判定电路取消指示开始前一指令的动作的开始信号。 此外，条件执行决定部分或电路判断存储在通用标志中的条件数据是否等于存储在执行条件字段中的条件，并且旁路控制部分根据控制部分控制旁路和数据通过用于数据传送操作 条件执行决定部分的决策结果。

公开(公告)号：US5996070A

公开(公告)日：1999-11-30

申请号：US783445

申请日：1997-01-16

Applicant: Akira Yamada ,  Toyohiko Yoshida ,  Toru Kengaku

Inventor： Akira Yamada ,  Toyohiko Yoshida ,  Toru Kengaku

IPC: G06F9/32 ,  G06F9/38 ,  G06F9/30

CPC classification number: G06F9/30094 ,  G06F9/30058 ,  G06F9/30072

Abstract: A 3-bit condition execution field in an condition execution instruction stores an encoded value obtained by encoding a condition stored in an general purpose flag indicating to execute the condition execution instruction. A microprocessor has an instruction decode unit 2 comprising a condition execution decode section 401 for decoding a value in the condition execution field and a condition execution judgement section 402 for judging whether or not the decoded result from the condition execution decode section 401 is equal to a condition stored in general purpose flags, and outputting the indication to execute the condition execution instruction when both are equal.

Abstract translation: 条件执行指令中的3位条件执行字段存储通过编码存储在指示执行条件执行指令的通用标志中的条件而获得的编码值。 微处理器具有指令解码单元2，其包括用于解码条件执行区域中的值的条件执行解码单元401和条件执行判断单元402，判定来自条件执行解码单元401的解码结果是否等于 条件存储在通用标志中，并且当两者相等时，输出指示以执行条件执行指令。

公开(公告)号：US5941984A

公开(公告)日：1999-08-24

申请号：US857461

申请日：1997-05-16

Applicant: Atsushi Mohri ,  Akira Yamada ,  Toyohiko Yoshida

Inventor： Atsushi Mohri ,  Akira Yamada ,  Toyohiko Yoshida

IPC: G06F9/38 ,  G06F15/16

CPC classification number: G06F9/3828 ,  G06F9/3889

Abstract: A VLIW microprocessor in which bypaths for transferring data among pipelines are incorporated between a plurality of execution units such as a memory access unit and an integer operation unit. The data on the bypaths is directly transferred to target units according to a control signal generated by a bypath processing control circuit.

Abstract translation: 一种VLIW微处理器，其中用于在管线之间传送数据的逐行路径被并入在诸如存储器存取单元和整数运算单元的多个执行单元之间。 根据由路径处理控制电路产生的控制信号，将路径上的数据直接传送到目标单元。

公开(公告)号：US06408385B1

公开(公告)日：2002-06-18

申请号：US09602830

申请日：2000-06-23

Applicant: Masahito Matsuo ,  Toyohiko Yoshida

Inventor： Masahito Matsuo ,  Toyohiko Yoshida

IPC: G06F940

CPC classification number: G06F9/3806 ,  G06F9/30054 ,  G06F9/321 ,  G06F9/3842 ,  G06F9/3867

Abstract: A data processor in accordance with the present invention makes it possible to perform pre-branch processing with respect to a return address in the initial stage of pipeline processing also on a subroutine return instruction, and therefore by providing a stack memory (PC stack) dedicated to a program counter (PC) for storing only return addresses of the subroutine return instruction, in executing a subroutine call instruction in an execution stage of a pipeline processing mechanism, the return address from the subroutine is pushed to the PC stack, and the pre-branch processing is performed to the address popped from the PC stack in decoding the subroutine return instruction in an instruction decoding stage.

Abstract translation: 根据本发明的数据处理器使得可以在流水线处理的初始阶段对子程序返回指令执行关于返回地址的预分支处理，因此通过提供专用的堆栈存储器（PC堆栈） 到用于仅存储子程序返回指令的返回地址的程序计数器（PC），在执行流水线处理机构的执行阶段中的子程序调用指令时，将子程序的返回地址推送到PC堆栈， 在指令解码阶段对子例程返回指令进行解码时，对从PC堆栈弹出的地址进行分支处理。

公开(公告)号：US06333571B1

公开(公告)日：2001-12-25

申请号：US09577969

申请日：2000-05-25

Applicant: Eiichi Teraoka ,  Toyohiko Yoshida

Inventor： Eiichi Teraoka ,  Toyohiko Yoshida

IPC: H01H4700

CPC classification number: H03K19/0013 ,  H01L27/092 ,  Y10T307/76 ,  Y10T307/826

Abstract: In accordance with selection signals corresponding to an operation mode from a mode detection circuit, the voltage levels of back gate voltages applied to the back gates of MOS transistors included in internal circuitry are selected, by the selection signals, among the voltages from voltage generation circuits for generating a plurality of voltages having different voltage levels. The threshold voltage and the drive current of the MOS transistor are adjusted in accordance with the operation mode, and the semiconductor integrated circuit device which operates at high speed with low current consumption can be achieved.

Abstract translation: 根据与来自模式检测电路的操作模式对应的选择信号，通过选择信号选择施加到内部电路中的MOS晶体管的背栅极的背栅电压的电压电平，来自电压产生电路 用于产生具有不同电压电平的多个电压。 根据操作模式调整MOS晶体管的阈值电压和驱动电流，并且可以实现以低电流消耗高速运行的半导体集成电路器件。

公开(公告)号：US6115806A

公开(公告)日：2000-09-05

申请号：US56650

申请日：1998-04-08

Applicant: Toyohiko Yoshida

Inventor： Toyohiko Yoshida

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F3/30

CPC classification number: G06F9/30167 ,  G06F9/30145 ,  G06F9/3842 ,  G06F9/3853 ,  G06F9/3885

Abstract: In a data processor, using a format field which specifies the number of operation fields of an instruction code and an order of execution of operations, the number of operations and the order of operation executions are flexibly controlled and the necessity of a null operation is reduced, and decoders operate in parallel each decoding only one operation having a specific function which has a dependency on an operation execution mechanism, so that the operation fields of the instruction code are decoded in parallel by a number of decoders. While the data processor is basically a VLIW type data processor, more types of operations can be specified by the operation fields, and coding efficiency of instructions is improved since the number of operation fields and the order of operation executions are flexibly controlled and the necessity of a null operation is reduced by means of the format field which specifies the number of the operation and the order of the operation executions.

Abstract translation: 在数据处理器中，使用指定指令代码的操作字段的数量的格式字段和操作的执行顺序，灵活地控制操作次数和操作执行顺序，并且减少空操作的必要性 并且解码器并行操作，每个仅解码具有与操作执行机构相关的特定功能的一个操作，使得指令代码的操作字段由多个解码器并行解码。 虽然数据处理器基本上是一个VLIW型数据处理器，但操作领域可以指定更多类型的操作，并且由于操作字段的数量和操作执行的顺序被灵活地控制，并且必须 通过指定操作次数和操作执行顺序的格式字段来减少空操作。