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    Integrated structures
    1.
    发明授权
    Integrated structures 有权

    公开(公告)号：US11081495B2

    公开(公告)日：2021-08-03

    申请号：US16438334

    申请日：2019-06-11

    Applicant: Micron Technology, Inc.

    Inventor： Justin B. Dorhout ,  David Daycock ,  Kunal R. Parekh ,  Martin C. Roberts ,  Yushi Hu

    IPC: H01L29/76 ,  H01L27/115 ,  H01L27/11582 ,  H01L29/66 ,  H01L29/78

    Abstract: Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and vertically-stacked conductive levels over the select device gate material. Vertically-extending monolithic channel material is adjacent the select device gate material and the conductive levels. The monolithic channel material contains a lower segment adjacent the select device gate material and an upper segment adjacent the conductive levels. A first vertically-extending region is between the lower segment of the monolithic channel material and the select device gate material. The first vertically-extending region contains a first material. A second vertically-extending region is between the upper segment of the monolithic channel material and the conductive levels. The second vertically-extending region contains a material which is different in composition from the first material.

    NAND memory arrays
    2.
    发明授权
    NAND memory arrays 有权

    公开(公告)号：US10431591B2

    公开(公告)日：2019-10-01

    申请号：US15422307

    申请日：2017-02-01

    Applicant: Micron Technology, Inc.

    Inventor： Akira Goda ,  Yushi Hu

    IPC: H01L27/115 ,  H01L27/11582 ,  H01L21/28

    Abstract: Some embodiments include a NAND memory array which has a vertical stack of alternating insulative levels and wordline levels. The wordline levels have terminal ends corresponding to control gate regions. Charge-trapping material is along the control gate regions of the wordline levels, and is spaced form the control gate regions by charge-blocking material. The charge-trapping material along vertically adjacent wordline levels is spaced by intervening regions through which charge migration is impeded. Channel material extends vertically along the stack and is spaced from the charge-trapping material by charge-tunneling material. Some embodiments include methods of forming NAND memory arrays.

    Integrated Assemblies and Methods of Forming Assemblies
    4.
    发明申请
    Integrated Assemblies and Methods of Forming Assemblies 审中-公开

    公开(公告)号：US20190198324A1

    公开(公告)日：2019-06-27

    申请号：US16292021

    申请日：2019-03-04

    Applicant: Micron Technology, Inc.

    Inventor： Yushi Hu ,  Shu Qin

    IPC: H01L21/225 ,  H01L21/28 ,  H01L27/11556 ,  H01L27/11582

    CPC classification number: H01L21/2253 ,  H01L21/28 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11556 ,  H01L27/11582

    Abstract: Some embodiments include an integrated assembly having a first semiconductor structure containing heavily-doped silicon, a germanium-containing interface material over the first semiconductor structure, and a second semiconductor structure over the germanium-containing interface material. The second semiconductor structure has a heavily-doped lower region adjacent the germanium-containing interface material and has a lightly-doped upper region above the heavily-doped lower region. The lightly-doped upper region and heavily-doped lower region are majority doped to a same dopant type, and join to one another along a boundary region. Some embodiments include an integrated assembly having germanium oxide between a first silicon-containing structure and a second silicon-containing structure. Some embodiments include methods of forming assemblies.

    Integrated Assemblies and Methods of Forming Assemblies
    6.
    发明申请
    Integrated Assemblies and Methods of Forming Assemblies 审中-公开

    公开(公告)号：US20170125426A1

    公开(公告)日：2017-05-04

    申请号：US14927217

    申请日：2015-10-29

    Applicant: Micron Technology, Inc.

    Inventor： Yushi Hu ,  Shu Qin

    IPC: H01L27/115

    CPC classification number: H01L21/2253 ,  H01L21/28 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11556 ,  H01L27/11582

    Abstract: Some embodiments include an integrated assembly having a first semiconductor structure containing heavily-doped silicon, a germanium-containing interface material over the first semiconductor structure, and a second semiconductor structure over the germanium-containing interface material. The second semiconductor structure has a heavily-doped lower region adjacent the germanium-containing interface material and has a lightly-doped upper region above the heavily-doped lower region. The lightly-doped upper region and heavily-doped lower region are majority doped to a same dopant type, and join to one another along a boundary region. Some embodiments include an integrated assembly having germanium oxide between a first silicon-containing structure and a second silicon-containing structure. Some embodiments include methods of forming assemblies.

    GATE STACKS
    7.
    发明申请
    GATE STACKS 审中-公开
    门盖

    公开(公告)号：US20160308018A1

    公开(公告)日：2016-10-20

    申请号：US14688387

    申请日：2015-04-16

    Applicant: Micron Technology, Inc.

    Inventor： Yushi Hu ,  John Mark Meldrim ,  Eric Blomiley ,  Everett Allen McTeer ,  Matthew J. King

    IPC: H01L29/49 ,  H01L21/28 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78

    CPC classification number: H01L29/4933 ,  H01L21/28061 ,  H01L21/28097 ,  H01L29/0649 ,  H01L29/4975 ,  H01L29/66477 ,  H01L29/78

    Abstract: Some embodiments disclose a gate stack having a gate (e.g., polysilicon (poly) material) horizontally between shallow trench isolations (STIs), a tungsten silicide (WSix) material over the gate and the STIs, and a tungsten silicon nitride (WSiN) material on a top surface of the WSix material. Some embodiments disclose a gate stack having a gate between STIs, a first WSix material over the gate and the STIs, a WSiN interlayer material on a top surface of the first WSix material, and a second WSix material on a top surface of the WSiN interlayer material. Additional embodiments are disclosed.

    Abstract translation: 一些实施例公开了在栅极和STI之间的浅沟槽隔离（STI），硅化钨（WSix）材料之间水平地具有栅极（例如，多晶硅（多晶）材料）的栅极堆叠以及氮化钨（WSiN）材料 在WSix材料的顶面。 一些实施例公开了一种栅极堆叠，其具有在STI之间的栅极，栅极上的第一WSix材料和STI，在第一WSix材料的顶表面上的WSiN夹层材料，以及在WSiN中间层的顶表面上的第二WSix材料 材料。 公开了其他实施例。

    MEMORY CELL PILLAR INCLUDING SOURCE JUNCTION PLUG
    10.
    发明申请
    MEMORY CELL PILLAR INCLUDING SOURCE JUNCTION PLUG 有权
    存储单元支柱，包括源结点插头

    公开(公告)号：US20160133638A1

    公开(公告)日：2016-05-12

    申请号：US14536021

    申请日：2014-11-07

    Applicant: Micron Technology, Inc.

    Inventor： Fatma Arzum Simsek-Ege ,  Krishna K. Parat ,  Luan C. Tran ,  Meng-Wei Kuo ,  Yushi Hu

    IPC: H01L27/115

    CPC classification number: H01L27/11524 ,  H01L21/8221 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/1158 ,  H01L27/11582

    Abstract: Some embodiments include apparatuses and methods having a source material, a dielectric material over the source material, a select gate material over the dielectric material, a memory cell stack over the select gate material, a conductive plug located in an opening of the dielectric material and contacting a portion of the source material, and a channel material extending through the memory cell stack and the select gate material and contacting the conductive plug.

    Abstract translation: 一些实施例包括具有源材料，源材料上方的介电材料，介电材料上方的选择栅极材料，选择栅极材料上方的存储单元堆叠，位于介电材料的开口中的导电插塞的装置和方法，以及 接触源材料的一部分，以及延伸穿过存储单元堆叠和选择栅极材料并与导电插塞接触的沟道材料。

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