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    DEVICE HAVING MULTIPLE CHANNELS WITH CALIBRATION CIRCUIT SHARED BY MULTIPLE CHANNELS
    2.
    发明申请
    DEVICE HAVING MULTIPLE CHANNELS WITH CALIBRATION CIRCUIT SHARED BY MULTIPLE CHANNELS 有权
    具有多个通道共享的校准电路的多通道器件

    公开(公告)号：US20150340069A1

    公开(公告)日：2015-11-26

    申请号：US14695837

    申请日：2015-04-24

    申请人： Micron Technology, Inc.

    发明人： TETSUYA ARAI ,  Junki Taniguchi

    IPC分类号： G11C7/04

    CPC分类号： G11C7/04 ,  G11C5/025 ,  G11C11/401 ,  G11C11/4093 ,  G11C29/021 ,  G11C29/025 ,  G11C29/028 ,  G11C2207/105 ,  G11C2207/2254 ,  H03K19/018507 ,  H03K19/018585

    摘要： An apparatus includes a first channel, a second channel and a calibration circuit. The first channel includes a first command control circuit. The second channel includes a second command control circuit independent of the first command control circuit. The calibration circuit is shared by the first channel and the second channel to generate a calibration code responsive to a calibration command generated responsive to a first calibration command from the first command control circuit and a second calibration command from the second command control circuit.

    摘要翻译： 一种装置包括第一通道，第二通道和校准电路。 第一通道包括第一命令控制电路。 第二通道包括独立于第一命令控制电路的第二命令控制电路。 所述校准电路由所述第一通道和所述第二通道共用，以响应于响应于来自所述第一命令控制电路的第一校准命令产生的校准命令和来自所述第二命令控制电路的第二校准命令产生校准代码。

    APPARATUS AND METHOD FOR STANDBY CURRENT CONTROL OF SIGNAL PATH
    4.
    发明申请
    APPARATUS AND METHOD FOR STANDBY CURRENT CONTROL OF SIGNAL PATH 审中-公开

    公开(公告)号：US20170366184A1

    公开(公告)日：2017-12-21

    申请号：US15690968

    申请日：2017-08-30

    申请人： Micron Technology, Inc.

    发明人： TETSUYA ARAI

    IPC分类号： H03K19/00 ,  H03K19/003

    CPC分类号： H03K19/0013 ,  H03K19/0016 ,  H03K19/00384

    摘要： Apparatuses and methods for standby current control of a signal path in a semiconductor device are described. An example apparatus includes: first and second logic gates coupled in series; a first circuit coupled between the first logic gate and a power supply line that activates the first logic gate responsive to a first control signal; and a second circuit coupled between the second logic gate and the power supply line that activates the second logic gate responsive to a second control signal that is different from the first control signal.

    SEMICONDUCTOR MEMORY DEVICE INCLUDING OUTPUT BUFFER
    5.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE INCLUDING OUTPUT BUFFER 审中-公开
    半导体存储器件，包括输出缓冲器

    公开(公告)号：US20150323971A1

    公开(公告)日：2015-11-12

    申请号：US14705762

    申请日：2015-05-06

    申请人： Micron Technology, Inc.

    发明人： TETSUYA ARAI ,  Junki Taniguchi

    IPC分类号： G06F1/26

    CPC分类号： G11C7/1057 ,  G01R31/3191 ,  G06F1/266 ,  G11C2207/2254

    摘要： An apparatus includes an external terminal, an output circuit having an impedance corresponding to a code signal, and a calibration circuit configured to produce the code signal responsive to a comparison of a voltage at the external terminal with a reference voltage, the comparison performed by a first cycle period in a first mode and by a second cycle which is longer than the first cycle period in a second mode.

    摘要翻译： 一种装置包括外部端子，具有对应于代码信号的阻抗的输出电路，以及校准电路，其被配置为响应于外部端子处的电压与参考电压的比较而产生代码信号，所述比较由 在第一模式中的第一循环周期和在第二模式中比第一循环周期长的第二循环。

    HIGH SPEED SIGNAL ADJUSTMENT CIRCUIT
    6.
    发明申请
    HIGH SPEED SIGNAL ADJUSTMENT CIRCUIT 审中-公开

    公开(公告)号：US20200304114A1

    公开(公告)日：2020-09-24

    申请号：US16358568

    申请日：2019-03-19

    申请人： MICRON TECHNOLOGY, INC.

    发明人： TETSUYA ARAI ,  JUNKI TANIGUCHI

    IPC分类号： H03K5/135 ,  H03K3/037 ,  H03M9/00 ,  H03K17/687 ,  G11C7/10

    摘要： Disclosed herein is an apparatus that includes a data serializer including a plurality of first buffer circuits configured to receive a plurality of data, respectively, and a second buffer circuit configured to serialize the plurality of data provided from the plurality of first buffer circuits. At least one of the plurality of first buffer circuits and the second buffer circuit includes: a first circuit configured to drive a first signal node to one of first and second logic levels based on an input signal, the first circuit including a first adjustment circuit configured to adjust a driving capability of the first circuit when the first circuit drives the first signal node to the first logic level, and a second circuit configured to drive the first signal node to other of the first and second logic levels.

    APPARATUS AND METHOD FOR STANDBY CURRENT CONTROL OF SIGNAL PATH
    7.
    发明申请
    APPARATUS AND METHOD FOR STANDBY CURRENT CONTROL OF SIGNAL PATH 有权

    公开(公告)号：US20170214403A1

    公开(公告)日：2017-07-27

    申请号：US15006646

    申请日：2016-01-26

    申请人： MICRON TECHNOLOGY, INC.

    发明人： TETSUYA ARAI

    IPC分类号： H03K19/00 ,  H03K19/003

    CPC分类号： H03K19/0013 ,  H03K19/0016 ,  H03K19/00384

    摘要： Apparatuses and methods for standby current control of a signal path in a semiconductor device are described. An example apparatus includes: first and second logic gates coupled in series; a first circuit coupled between the first logic gate and a power supply line that activates the first logic gate responsive to a first control signal; and a second circuit coupled between the second logic gate and the power supply line that activates the second logic gate responsive to a second control signal that is different from the first control signal.