公开(公告)号：US20150123206A1

公开(公告)日：2015-05-07

申请号：US14450445

申请日：2014-08-04

Applicant: MediaTek Inc.

Inventor： Cheng-Chou HUNG ,  Tung-Hsing LEE ,  Bernard Mark TENBROEK ,  Rong-Tang CHEN

IPC: H01L29/78 ,  H01L29/49 ,  H01L29/10 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/783 ,  H01L29/0649 ,  H01L29/1095 ,  H01L29/4238 ,  H01L29/4975 ,  H01L29/78615 ,  H01L29/78654 ,  H01L29/78657

Abstract: The invention provides a body-contact metal-oxide-semiconductor field effect transistor (MOSFET) device. The body-contact MOSFET device includes a substrate. An active region is disposed on the substrate. A gate strip is extended along a first direction disposed on a first portion of the active region. A source doped region and a drain doped region are disposed on a second portion and a third portion of the active region, adjacent to opposite sides of the gate strip. The opposite sides of the gate strip are extended along the first direction. A body-contact doped region is disposed on a fourth portion of the active region. The body-contact doped region is separated from the gate strip by a fifth portion of the active region. The fifth portion is not covered by any silicide features.

Abstract translation: 本发明提供一种体接触金属氧化物半导体场效应晶体管（MOSFET）器件。 体接触MOSFET器件包括衬底。 有源区设置在基板上。 栅极条沿着设置在有源区域的第一部分上的第一方向延伸。 源极掺杂区域和漏极掺杂区域设置在与栅极条的相对侧相邻的有源区域的第二部分和第三部分上。 栅极条的相对侧沿第一方向延伸。 体接触掺杂区域设置在有源区域的第四部分上。 体接触掺杂区域与有源区域的第五部分与栅极条分离。 第五部分不被任何硅化物特征覆盖。

公开(公告)号：US20170084525A1

公开(公告)日：2017-03-23

申请号：US15365394

申请日：2016-11-30

Applicant: MediaTek Inc.

Inventor： Cheng-Chou HUNG ,  Ming-Tzong YANG ,  Tung-Hsing LEE ,  Wei-Che HUANG ,  Yu-Hua HUANG ,  Tzu-Hung LIN

IPC: H01L23/498 ,  H01L21/768 ,  H01L29/06 ,  H01L21/761

CPC classification number: H01L21/76898 ,  H01L21/761 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/11 ,  H01L29/0619 ,  H01L29/0623 ,  H01L2224/13 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor package structure having a substrate, wherein the substrate has a front side and a back side, a through silicon via (TSV) interconnect structure formed in the substrate, and a first guard ring doped region and a second guard ring doped region formed in the substrate. The second guard ring doped region is disposed between the first guard ring doped region and the TSV interconnect structure.

公开(公告)号：US20150162267A1

公开(公告)日：2015-06-11

申请号：US14621682

申请日：2015-02-13

Applicant: MediaTek Inc.

Inventor： Ming-Tzong YANG ,  Cheng-Chou HUNG ,  Tung-Hsing LEE ,  Wei-Che HUANG ,  Yu-Hua HUANG

IPC: H01L23/48 ,  H01L23/00

CPC classification number: H01L21/76898 ,  H01L21/02107 ,  H01L21/268 ,  H01L21/30625 ,  H01L23/481 ,  H01L23/5227 ,  H01L23/66 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L31/18 ,  H01L2223/6616 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/11 ,  H01L2924/12042 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An electronic device package has a base and an electronic device chip mounted on the base. The electronic device chip includes a semiconductor substrate having a front side and a back side, a electronic component disposed on the front side of the semiconductor substrate, an interconnect structure disposed on the electronic component, a through hole formed through the semiconductor substrate from the back side of the semiconductor substrate, connecting to the interconnect structure, and a TSV structure disposed in the through hole. The interconnect structure is electrically connected to the RF component, and a thickness of the semiconductor substrate is less than that of the interconnect structure.

Abstract translation: 电子器件封装具有安装在基座上的基座和电子器件芯片。 电子设备芯片包括具有前侧和后侧的半导体衬底，设置在半导体衬底的前侧的电子部件，设置在电子部件上的互连结构，从背面穿过半导体衬底形成的通孔 连接到互连结构的半导体衬底的一侧以及设置在通孔中的TSV结构。 互连结构电连接到RF部件，并且半导体衬底的厚度小于互连结构的厚度。

公开(公告)号：US20150162242A1

公开(公告)日：2015-06-11

申请号：US14621703

申请日：2015-02-13

Applicant: MediaTek Inc.

Inventor： Ming-Tzong YANG ,  Cheng-Chou HUNG ,  Tung-Hsing LEE ,  Wei-Che HUANG ,  Yu-Hua HUANG

IPC: H01L21/768 ,  H01L21/268 ,  H01L21/306 ,  H01L23/00

CPC classification number: H01L21/76898 ,  H01L21/02107 ,  H01L21/268 ,  H01L21/30625 ,  H01L23/481 ,  H01L23/5227 ,  H01L23/66 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L31/18 ,  H01L2223/6616 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/11 ,  H01L2924/12042 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method for fabricating a electronic device package provides a electronic device chip, wherein the electronic device chip includes a semiconductor substrate having a front side and a back side, wherein the semiconductor substrate has a first thickness, an electronic component disposed on the front side of the semiconductor substrate, and an interconnect structure disposed on the electronic component. The method further performs a thinning process to remove a portion of the semiconductor substrate from the back side thereof The method then removes a portion of the thinned semiconductor substrate and a portion of a dielectric layer of the interconnect structure from a back side of the thinned semiconductor substrate until a first metal layer pattern of the interconnect structure is exposed, thereby forming a through hole. Finally, the method forms a TSV structure in the through hole, and mounts the electronic device chip on a base.

Abstract translation: 一种制造电子器件封装的方法，提供了一种电子器件芯片，其中电子器件芯片包括具有正面和背面的半导体衬底，其中半导体衬底具有第一厚度，电子部件设置在第一厚度的前侧 半导体衬底和布置在电子部件上的互连结构。 该方法还进行薄膜化处理以从背面去除半导体衬底的一部分。然后，该方法从薄化半导体的背面去除一部分减薄的半导体衬底和互连结构的介电层的一部分 衬底，直到互连结构的第一金属层图案被暴露，从而形成通孔。 最后，该方法在通孔中形成TSV结构，并将电子设备芯片安装在基座上。

公开(公告)号：US20240339447A1

公开(公告)日：2024-10-10

申请号：US18603426

申请日：2024-03-13

Applicant: MEDIATEK INC.

Inventor： Tzung-Lin LI ,  Yuan-Fu CHUNG ,  Tung-Hsing LEE

IPC: H01L27/02 ,  H01L29/868

CPC classification number: H01L27/0255 ,  H01L29/868

Abstract: An electrostatic discharge protection device is provided. The electrostatic discharge protection device includes a P-type semiconductor substrate, P-type and N-type well regions, a deep N-type well region, first N-type and P-type doped regions, second N-type and P-type doped regions. The P-type and N-type well regions are located in the P-type semiconductor substrate. The deep N-type well region is located in the P-type semiconductor substrate and below the P-type well region. The first N-type and P-type doped regions are located on the P-type well region. The second N-type and P-type doped regions are located on the N-type well region. The first P-type doped region is electrically connected to the second N-type doped region.

公开(公告)号：US20170084488A1

公开(公告)日：2017-03-23

申请号：US15365435

申请日：2016-11-30

Applicant: MediaTek Inc.

Inventor： Cheng-Chou HUNG ,  Ming-Tzong YANG ,  Tung-Hsing LEE ,  Wei-Che HUANG ,  Yu-Hua HUANG ,  Tzu-Hung LIN

IPC: H01L21/768 ,  H01L23/00 ,  H01L29/06 ,  H01L23/48 ,  H01L21/761

CPC classification number: H01L21/76898 ,  H01L21/761 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/11 ,  H01L29/0619 ,  H01L29/0623 ,  H01L2224/13 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a semiconductor package structure is provided. The method for forming a semiconductor package structure includes providing a substrate, wherein the substrate has a front side and a back side, forming a first guard ring doped region and a second guard ring doped region in the substrate, wherein the first guard ring doped region and the second guard ring doped region have different conductive types, forming a trench through the substrate from a back side of the substrate, conformally forming an insulating layer lining the back side of the substrate, a bottom surface and sidewalls of the trench, removing a portion of the insulating layer on the back side of the substrate to form a through via, and forming a conductive material in the through via, wherein a through silicon via (TSV) interconnect structure is formed by the insulating layer and the conductive material.

公开(公告)号：US20140070346A1

公开(公告)日：2014-03-13

申请号：US13790060

申请日：2013-03-08

Applicant: MEDIATEK INC.

Inventor： Ming-Tzong YANG ,  Cheng-Chou HUNG ,  Tung-Hsing LEE ,  Wei-Che HUANG ,  Yu-Hua HUANG

IPC: H01L23/522 ,  H01L31/18

CPC classification number: H01L21/76898 ,  H01L21/02107 ,  H01L21/268 ,  H01L21/30625 ,  H01L23/481 ,  H01L23/5227 ,  H01L23/66 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L31/18 ,  H01L2223/6616 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/11 ,  H01L2924/12042 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00

Abstract: The invention provides a radio-frequency (RF) device package and a method for fabricating the same. An exemplary embodiment of a radio-frequency (RF) device package includes a base, wherein a radio-frequency (RF) device chip is mounted on the base. The RF device chip includes a semiconductor substrate having a front side and a back side. A radio-frequency (RF) component is disposed on the front side of the semiconductor substrate. An interconnect structure is disposed on the RF component, wherein the interconnect structure is electrically connected to the RF component, and a thickness of the semiconductor substrate is less than that of the interconnect structure. A through hole is formed through the semiconductor substrate from the back side of the semiconductor substrate, and is connected to the interconnect structure. A TSV structure is disposed in the through hole.

Abstract translation: 本发明提供一种射频（RF）器件封装及其制造方法。 射频（RF）器件封装的示例性实施例包括基座，其中射频（RF）器件芯片安装在基座上。 RF器件芯片包括具有前侧和后侧的半导体衬底。 射频（RF）部件设置在半导体衬底的前侧。 互连结构设置在RF部件上，其中互连结构电连接到RF部件，并且半导体衬底的厚度小于互连结构的厚度。 从半导体衬底的背面穿过半导体衬底形成一个通孔，并连接到互连结构。 TSV结构设置在通孔中。

公开(公告)号：US20160211194A1

公开(公告)日：2016-07-21

申请号：US14601440

申请日：2015-01-21

Applicant: MediaTek Inc.

Inventor： Cheng-Chou HUNG ,  Ming-Tzong YANG ,  Tung-Hsing LEE ,  Wei-Che HUANG ,  Yu-Hua HUANG ,  Tzu-Hung LIN

IPC: H01L23/48 ,  H01L21/761 ,  H01L21/768 ,  H01L29/06

CPC classification number: H01L21/76898 ,  H01L21/761 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/11 ,  H01L29/0619 ,  H01L29/0623 ,  H01L2224/13 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor package structure and method for forming the same are provided. The semiconductor package structure includes a substrate and the substrate has a front side and a back side. The semiconductor package structure includes a through silicon via (TSV) interconnect structure formed in the substrate; and a first guard ring doped region and a second guard ring doped region formed in the substrate, and the first guard ring doped region and the second guard ring doped region are adjacent to the TSV interconnect structure.

Abstract translation: 提供一种半导体封装结构及其形成方法。 半导体封装结构包括衬底，并且衬底具有正面和背面。 半导体封装结构包括在衬底中形成的穿硅通孔（TSV）互连结构; 以及形成在所述衬底中的第一保护环掺杂区域和第二保护环掺杂区域，并且所述第一保护环掺杂区域和所述第二保护环掺杂区域与所述TSV互连结构相邻。

公开(公告)号：US20160028359A1

公开(公告)日：2016-01-28

申请号：US14874888

申请日：2015-10-05

Applicant: MediaTek Inc.

Inventor： Ming-Tzong YANG ,  Cheng-Chou HUNG ,  Tung-Hsing LEE ,  Wei-Che HUANG

IPC: H03H7/01

CPC classification number: H03H7/0115 ,  H01P1/20381 ,  H01P7/082 ,  H03H3/00

Abstract: An implementation of the invention is directed to a passive device cell having a substrate layer, and intermediary layer formed above the substrate layer, and a passive device formed above the intermediary layer. The intermediary layer includes a plurality of LC resonators and a plurality of segmented conductive lines, wherein the plurality of segmented conductive lines are disposed between the plurality of LC resonators.

Abstract translation: 本发明的实施例涉及一种无源器件单元，其具有衬底层，以及形成在衬底层上方的中间层，以及形成在中间层上方的无源器件。 中间层包括多个LC谐振器和多个分段导电线，其中多个分段导线设置在多个LC谐振器之间。

公开(公告)号：US20140312470A1

公开(公告)日：2014-10-23

申请号：US14320725

申请日：2014-07-01

Applicant: MediaTek Inc.

Inventor： Cheng-Chou HUNG ,  Tung-Hsing LEE ,  Yu-Hua HUANG ,  Ming-Tzong YANG

IPC: H01L23/00

CPC classification number: H01L23/562 ,  H01L23/564 ,  H01L23/585 ,  H01L27/0805 ,  H01L29/94 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type having a chip region enclosed by a seal ring region. An insulating layer is on the semiconductor substrate. A seal ring structure is embedded in the insulating layer corresponding to the seal ring region. And, a plurality of doping regions are located beneath the first seal ring structure.

Abstract translation: 半导体器件包括具有由密封环区域包围的芯片区域的第一导电类型的半导体衬底。 绝缘层位于半导体衬底上。 密封环结构埋设在对应于密封圈区域的绝缘层中。 并且，多个掺杂区域位于第一密封环结构下方。