公开(公告)号：US5965923A

公开(公告)日：1999-10-12

申请号：US26235

申请日：1998-02-19

Applicant: Kirk D. Prall ,  Mike P. Violette

Inventor： Kirk D. Prall ,  Mike P. Violette

IPC: H01L21/331 ,  H01L21/8222 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/082 ,  H01L29/735 ,  H01L27/102 ,  H01L29/70 ,  H01L31/11

CPC classification number: H01L29/6625 ,  H01L21/8222 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/082 ,  H01L29/735

Abstract: A substantially concentric lateral bipolar transistor and the method of forming same. A base region is disposed about a periphery of an emitter region, and a collector region is disposed about a periphery of the base region to form the concentric lateral bipolar transistor of the invention. A gate overlies the substrate and at least a portion of the base region. At least one electrical contact is formed connecting the base and the gate, although a plurality of contacts may be formed. A further bipolar transistor is formed according to the following method of the invention. A base region is formed in a substrate and a gate region is formed overlying at least a portion of the base region. Emitter and collector terminals are formed on opposed sides of the base region. The gate is used as a mask during first and second ion implants. During the first ion implant the ions bombard the substrate from a first direction to grade a base/emitter junction, and during the second ion implant ions bombard the substrate from a second direction to grade a base/collector junction. Aso a lateral bipolar transistor having a decreased base width as a result of implanting ions after fabrication of collector and emitter regions to enlarge the collector and emitter regions, thereby decreasing the base region and increasing gain.

Abstract translation: 基本同心的横向双极晶体管及其形成方法。 基极区域围绕发射极区域的周边设置，并且集电极区域围绕基极区域的周边设置以形成本发明的同心横向双极晶体管。 栅极覆盖衬底和基极区域的至少一部分。 形成连接基座和栅极的至少一个电触头，尽管可以形成多个触点。 根据本发明的以下方法形成另外的双极晶体管。 在基板中形成基极区域，并且形成覆盖基极区域的至少一部分的栅极区域。 发射极和集电极端子形成在基极区域的相对侧上。 在第一和第二离子注入期间，门用作掩模。 在第一离子注入期间，离子从第一方向轰击衬底以分级基极/发射极结，并且在第二离子注入期间，离子从第二方向轰击衬底以对基极/集电极结进行分级。 Aso是在制造集电极和发射极区域之后注入离子的结果，具有减小的基极宽度的横向双极晶体管，以扩大集电极和发射极区域，从而减小基极区域并增加增益。

公开(公告)号：US06166426A

公开(公告)日：2000-12-26

申请号：US233871

申请日：1999-01-20

Applicant: Kirk D. Prall ,  Mike P. Violette

Inventor： Kirk D. Prall ,  Mike P. Violette

IPC: H01L21/331 ,  H01L21/8222 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/082 ,  H01L29/735 ,  H01L27/102 ,  H01L29/70 ,  H01L31/11

CPC classification number: H01L29/6625 ,  H01L21/8222 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/082 ,  H01L29/735

Abstract: A substantially concentric lateral bipolar transistor and the method of forming same. A base region is disposed about a periphery of an emitter region, and a collector region is disposed about a periphery of the base region to form the concentric lateral bipolar transistor of the invention. A gate overlies the substrate and at least a portion of the base region. At least one electrical contact is formed connecting the base and the gate, although a plurality of contacts may be formed. A further bipolar transistor is formed according to the following method of the invention. A base region is formed in a substrate and a gate region is formed overlying at least a portion of the base region. Emitter and collector terminals are formed on opposed sides of the base region. The gage is used as a mask during first and second ion implants. During the first ion implant the ions bombard the substrate from a first direction to grade a base/emitter junction, and during the second ion implant ions bombard the substrate from a second direction to grade a base/collector junction. Also a lateral bipolar transistor having a decreased base width as a result of implanting ions after fabrication of collector and emitter regions to enlarge the collector and emitter regions, thereby decreasing the base region and increasing gain.

Abstract translation: 基本同心的横向双极晶体管及其形成方法。 基极区域围绕发射极区域的周边设置，并且集电极区域围绕基极区域的周边设置以形成本发明的同心横向双极晶体管。 栅极覆盖衬底和基极区域的至少一部分。 形成连接基座和栅极的至少一个电触头，尽管可以形成多个触点。 根据本发明的以下方法形成另外的双极晶体管。 在基板中形成基极区域，并且形成覆盖基极区域的至少一部分的栅极区域。 发射极和集电极端子形成在基极区域的相对侧上。 在第一和第二离子植入物期间，将量规用作掩模。 在第一离子注入期间，离子从第一方向轰击衬底以分级基极/发射极结，并且在第二离子注入期间，离子从第二方向轰击衬底以对基极/集电极结进行分级。 另外，作为在集电极和发射极区域制造之后注入离子的结果，具有减小的基极宽度的横向双极晶体管，以扩大集电极和发射极区域，从而减小基极区域并增加增益。

公开(公告)号：US06489665B2

公开(公告)日：2002-12-03

申请号：US09742706

申请日：2000-12-20

Applicant: Kirk D. Prall ,  Mike P. Violette

Inventor： Kirk D. Prall ,  Mike P. Violette

IPC: H01L27082

CPC classification number: H01L29/6625 ,  H01L21/8222 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/082 ,  H01L29/735

Abstract: A substantially concentric lateral bipolar transistor and the method of forming same. A base region is disposed about a periphery of an emitter region, and a collector region is disposed about a periphery of the base region to form the concentric lateral bipolar transistor of the invention. A gate overlies the substrate and at least a portion of the base region. At least one electrical contact is formed connecting the base and the gate, although a plurality of contacts may be formed. A further bipolar transistor is formed according to the following method of the invention. A base region is formed in a substrate and a gate region is formed overlying at least a portion of the base region. Emitter and collector terminals are formed on opposed sides of the base region. The gate is used as a mask during first and second ion implants. During the first ion implant the ions bombard the substrate from a first direction to grade a base/emitter junction, and during the second ion implant ions bombard the substrate from a second direction to grade a base/collector junction. Also a lateral bipolar transistor having a decreased base width as a result of implanting ions after fabrication of collector and emitter regions to enlarge the collector and emitter regions, thereby decreasing the base region and increasing gain.

Abstract translation: 基本同心的横向双极晶体管及其形成方法。 基极区域围绕发射极区域的周边设置，并且集电极区域围绕基极区域的周边设置以形成本发明的同心横向双极晶体管。 栅极覆盖衬底和基极区域的至少一部分。 形成连接基座和栅极的至少一个电触头，尽管可以形成多个触点。 根据本发明的以下方法形成另外的双极晶体管。 在基板中形成基极区域，并且形成覆盖基极区域的至少一部分的栅极区域。 发射极和集电极端子形成在基极区域的相对侧上。 在第一和第二离子注入期间，门用作掩模。 在第一离子注入期间，离子从第一方向轰击衬底以分级基极/发射极结，并且在第二离子注入期间，离子从第二方向轰击衬底以对基极/集电极结进行分级。 另外，作为在制造集电极和发射极区域之后注入离子的结果，具有减小的基极宽度的横向双极晶体管，以扩大集电极和发射极区域，从而减小基极区域并增加增益。

公开(公告)号：US6127236A

公开(公告)日：2000-10-03

申请号：US131454

申请日：1998-08-10

Applicant: Kirk D. Prall ,  Mike P. Violette

Inventor： Kirk D. Prall ,  Mike P. Violette

IPC: H01L21/331 ,  H01L21/8222 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/082 ,  H01L29/735

CPC classification number: H01L29/6625 ,  H01L21/8222 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/082 ,  H01L29/735

Abstract: A substantially concentric lateral bipolar transistor and the method of forming same. A base region is disposed about a periphery of an emitter region, and a collector region is disposed about a periphery of the base region to form the concentric lateral bipolar transistor of the invention. A gate overlies the substrate and at least a portion of the base region. At least one electrical contact is formed connecting the base and the gate, although a plurality of contacts may be formed. A further bipolar transistor is formed according to the following method of the invention. A base region is formed in a substrate and a gate region is formed overlying at least a portion of the base region. Emitter and collector terminals are formed on opposed sides of the base region. The gate is used as a mask during first and second ion implants. During the first ion implant the ions bombard the substrate from a first direction to grade a base/emitter junction, and during the second ion implant ions bombard the substrate from a second direction to grade a base/collector junction. Also a lateral bipolar transistor having a decreased base width as a result of implanting ions after fabrication of collector and emitter regions to enlarge the collector and emitter regions, thereby decreasing the base region and increasing gain.

Abstract translation: 基本同心的横向双极晶体管及其形成方法。 基极区域围绕发射极区域的周边设置，并且集电极区域围绕基极区域的周边设置以形成本发明的同心横向双极晶体管。 栅极覆盖基板和基极区域的至少一部分。 形成连接基座和栅极的至少一个电触头，尽管可以形成多个触点。 根据本发明的以下方法形成另外的双极晶体管。 在基板中形成基极区域，并且形成覆盖基极区域的至少一部分的栅极区域。 发射极和集电极端子形成在基极区域的相对侧上。 在第一和第二离子注入期间，门用作掩模。 在第一离子注入期间，离子从第一方向轰击衬底以分级基极/发射极结，并且在第二离子注入期间，离子从第二方向轰击衬底以对基极/集电极结进行分级。 另外，作为在集电极和发射极区域制造之后注入离子的结果，具有减小的基极宽度的横向双极晶体管，以扩大集电极和发射极区域，从而减小基极区域并增加增益。

公开(公告)号：US5945726A

公开(公告)日：1999-08-31

申请号：US766659

申请日：1996-12-16

Applicant: Kirk D. Prall ,  Mike P. Violette

Inventor： Kirk D. Prall ,  Mike P. Violette

IPC: H01L21/331 ,  H01L21/8222 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/082 ,  H01L29/735

CPC classification number: H01L29/6625 ,  H01L21/8222 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/082 ,  H01L29/735

Abstract: A substantially concentric lateral bipolar transistor having a base region that is disposed about a periphery of an emitter region, and a collector region that is disposed about a periphery of the base region to form the concentric lateral bipolar transistor of the invention. A gate overlies the substrate and at least a portion of the base region. At least one electrical contact is formed connecting the base and the gate, although a plurality of contacts may be formed. A further bipolar transistor is formed according to the following method of the invention. A base region is formed in a substrate and a gate region is formed overlying at least a portion of the base region. Emitter and collector terminals are formed on opposed sides of the base region. The gate is used as a mask during first and second ion implants. During the first ion implant the ions bombard the substrate from a first direction to grade a base/emitter junction, and during the second ion implant ions bombard the substrate from a second direction to grade a base/collector junction. Also a lateral bipolar transistor having a decreased base width as a result of implanting ions after fabrication of collector and emitter regions to enlarge the collector and emitter regions, thereby decreasing the base region and increasing gain.

Abstract translation: 具有围绕发射极区域的周边设置的基极区域的基本上同心的横向双极晶体管，以及围绕所述基极区域的周边设置的集电极区域，以形成本发明的同心横向双极晶体管。 栅极覆盖衬底和基极区域的至少一部分。 形成连接基座和栅极的至少一个电触头，尽管可以形成多个触点。 根据本发明的以下方法形成另外的双极晶体管。 在基板中形成基极区域，并且形成覆盖基极区域的至少一部分的栅极区域。 发射极和集电极端子形成在基极区域的相对侧上。 在第一和第二离子注入期间，门用作掩模。 在第一离子注入期间，离子从第一方向轰击衬底以分级基极/发射极结，并且在第二离子注入期间，离子从第二方向轰击衬底以对基极/集电极结进行分级。 另外，作为在集电极和发射极区域制造之后注入离子的结果，具有减小的基极宽度的横向双极晶体管，以扩大集电极和发射极区域，从而减小基极区域并增加增益。

公开(公告)号：US09142767B2

公开(公告)日：2015-09-22

申请号：US13234875

申请日：2011-09-16

Applicant: David H. Wells ,  D. V. Nirmal Ramaswamy ,  Kirk D. Prall

Inventor： David H. Wells ,  D. V. Nirmal Ramaswamy ,  Kirk D. Prall

IPC: H01L47/00 ,  H01L45/00 ,  H01L27/24

CPC classification number: H01L45/085 ,  G11C2213/73 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/142 ,  H01L45/143 ,  H01L45/146

Abstract: Resistive memory cells including an integrated select device and storage element and methods of forming the same are described herein. As an example, a resistive memory cell can include a select device structure including a Schottky interface, and a storage element integrated with the select device structure such that an electrode corresponding to the Schottky interface serves as a first electrode of the storage element. The storage element can include a storage material formed between the first electrode and a second electrode.

Abstract translation: 包括集成选择装置和存储元件的电阻式存储单元及其形成方法在此描述。 作为示例，电阻式存储单元可以包括包括肖特基接口的选择器件结构和与选择器件结构集成的存储元件，使得对应于肖特基界面的电极用作存储元件的第一电极。 存储元件可以包括形成在第一电极和第二电极之间的存储材料。

公开(公告)号：US08441056B2

公开(公告)日：2013-05-14

申请号：US12795906

申请日：2010-06-08

Applicant: Kirk D. Prall ,  Leonard Forbes

Inventor： Kirk D. Prall ,  Leonard Forbes

IPC: H01L29/72

CPC classification number: H01L27/11568 ,  G11C11/5692 ,  G11C16/0475 ,  H01L27/115

Abstract: An array of memory cells configured to store at least one bit per one F2 includes substantially vertical structures providing an electronic memory function spaced apart a distance equal to one half of a minimum pitch of the array. The structures providing the electronic memory function are configured to store more than one bit per gate. The array also includes electrical contacts to the memory cells including the substantially vertical structures. The cells can be programmed to have one of a number of charge levels trapped in the gate insulator adjacent to the first source/drain region such that the channel region has a first voltage threshold region (Vt1) and a second voltage threshold region (Vt2) and such that the programmed cell operates at reduced drain source current.

公开(公告)号：US20130088909A1

公开(公告)日：2013-04-11

申请号：US13269717

申请日：2011-10-10

Applicant: Zengtao T. Liu ,  Kirk D. Prall

Inventor： Zengtao T. Liu ,  Kirk D. Prall

IPC: G11C11/00 ,  G11C7/00

CPC classification number: G11C13/004 ,  G11C8/08 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/0033 ,  G11C13/0038 ,  G11C2013/0054 ,  G11C2013/0057 ,  G11C2013/0083 ,  G11C2213/77

Abstract: The apparatuses and methods described herein may operate to measure a voltage difference between a selected access line and a selected sense line associated with a selected cell of a plurality of memory cells of a memory array. The voltage difference may be compared with a reference voltage specified for a memory operation. A selection voltage(s) applied to the selected cell for the memory operation may be adjusted responsive to the comparison, such as to dynamically compensate for parasitic voltage drop.

公开(公告)号：US08351242B2

公开(公告)日：2013-01-08

申请号：US12893992

申请日：2010-09-29

Applicant: D. V. Nirmal Ramaswamy ,  Kirk D. Prall

Inventor： D. V. Nirmal Ramaswamy ,  Kirk D. Prall

IPC: G11C11/00 ,  G11C11/34 ,  H01L27/105

CPC classification number: H01L45/14 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146

Abstract: Some embodiments include electronic devices having two capacitors connected in series. The two capacitors share a common electrode. One of the capacitors includes a region of a semiconductor substrate and a dielectric between such region and the common electrode. The other of the capacitors includes a second electrode and ion conductive material between the second electrode and the common electrode. At least one of the first and second electrodes has an electrochemically active surface directly against the ion conductive material. Some embodiments include memory cells having two capacitors connected in series, and some embodiments include memory arrays containing such memory cells.

公开(公告)号：US08268692B2

公开(公告)日：2012-09-18

申请号：US13154618

申请日：2011-06-07

Applicant: Gurtej S. Sandhu ,  Kirk D. Prall

Inventor： Gurtej S. Sandhu ,  Kirk D. Prall

IPC: H01L21/336

CPC classification number: H01L21/28273 ,  B82Y10/00 ,  H01L29/42332

Abstract: A method of fabricating a memory cell including forming nanodots over a first dielectric layer and forming an intergate dielectric layer over the nanodots, where the intergate dielectric layer encases the nanodots. To form sidewalls of the memory cell, a portion of the intergate dielectric layer is removed with a dry etch, where the sidewalls include a location where a nanodot has been deposited. A spacing layer is formed over the sidewalls to cover the location where a nanodot has been deposited and the remaining portion of the intergate dielectric layer and the nanodots can be removed with an etch selective to the intergate dielectric layer.

Abstract translation: 一种制造存储单元的方法，包括在第一介电层上形成纳米点并在纳米点上形成隔间电介质层，其中隔间电介质层封装在纳米点上。 为了形成存储器单元的侧壁，隔离介电层的一部分用干蚀刻去除，其中侧壁包括已经沉积纳米点的位置。 在侧壁上形成间隔层以覆盖已经沉积纳米点的位置，并且可以用对栅极间电介质层选择性的蚀刻来去除间隔栅电介质层和纳米点的剩余部分。