知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

46 records (took 0.024 seconds)

    MEMORY SYSTEM AND METHOD OF CONTROLLING NONVOLATILE MEMORY
    1.
    发明公开
    MEMORY SYSTEM AND METHOD OF CONTROLLING NONVOLATILE MEMORY 审中-公开

    公开(公告)号：US20240295969A1

    公开(公告)日：2024-09-05

    申请号：US18592763

    申请日：2024-03-01

    Applicant: Kioxia Corporation

    Inventor： Suguru NISHIKAWA ,  Takehiko AMAKI ,  Shunichi IGAHARA ,  Toshikatsu HIDA ,  Yoshihisa KOJIMA

    IPC: G06F3/06

    CPC classification number: G06F3/0619 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679

    Abstract: According to an embodiment, a memory system includes a nonvolatile memory and a memory controller. The nonvolatile memory includes a first memory cell configured to nonvolatilely store data of a plurality of bits including a first bit and a second bit, and a second memory cell configured to nonvolatilely store data of at least one bit. The memory controller is configured to execute a save operation in accordance with reception of a command from a host, in the save operation, write first bit data to the second memory cell in a case where the first memory cell stores the first bit data as the first bit and does not store data as the second bit, and transmit, to the host, a completion response to the command after the first bit data has been written to the second memory cell.

    MEMORY SYSTEM AND METHOD OF CONTROLLING NONVOLATILE MEMORY
    6.
    发明申请
    MEMORY SYSTEM AND METHOD OF CONTROLLING NONVOLATILE MEMORY 有权

    公开(公告)号：US20220083264A1

    公开(公告)日：2022-03-17

    申请号：US17199586

    申请日：2021-03-12

    Applicant: Kioxia Corporation

    Inventor： Yoshihisa KOJIMA ,  Riki SUZUKI

    IPC: G06F3/06 ,  G06F12/06

    Abstract: A memory system includes a controller that transmits, to a memory chip, one first command set indicating a head of a third storage area being one of second storage areas, in a case where first data is read to a first buffer of the memory chip. The first data includes a plurality of first data segments having been stored in the second storage areas. The memory chip includes circuitry that outputs a second data segment and a third data segment to the controller in a period after the controller transmits the first command set to the memory chip before the controller transmits a second command set to the memory chip. The second data segment is a data segment having been stored in the third storage area. The third data segment is a data segment having been stored in a fourth storage area different from the third storage area.

    MEMORY SYSTEM
    7.
    发明申请
    MEMORY SYSTEM 有权

    公开(公告)号：US20210081276A1

    公开(公告)日：2021-03-18

    申请号：US16806131

    申请日：2020-03-02

    Applicant: KIOXIA CORPORATION

    Inventor： Riki SUZUKI ,  Toshikatsu HIDA ,  Yoshihisa KOJIMA ,  Takehiko AMAKI ,  Suguru NISHIKAWA

    IPC: G06F11/10 ,  G06F3/06

    Abstract: A memory system includes a nonvolatile memory, a buffer, and a controller. The buffer can temporarily store a plurality of data bits to be written to the nonvolatile memory. The controller can write the plurality of data bits, read from the buffer, to the nonvolatile memory; write a plurality of intermediate parity bits to the buffer, but not to the nonvolatile memory, wherein each of the plurality of intermediate parity bits is associated with an error correction process on each of the plurality of data bits; and write, to the nonvolatile memory, an accumulated parity bit that is an integration of the plurality of intermediate parity bits.

    MEMORY SYSTEM
    10.
    发明公开
    MEMORY SYSTEM 审中-公开

    公开(公告)号：US20230420060A1

    公开(公告)日：2023-12-28

    申请号：US18459501

    申请日：2023-09-01

    Applicant: KIOXIA CORPORATION

    Inventor： Tomoya KAMATA ,  Yoshihisa KOJIMA ,  Suguru NISHIKAWA

    IPC: G11C16/32 ,  G11C7/22

    CPC classification number: G11C16/32 ,  G11C7/22

    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller configured to cause the nonvolatile memory to execute a first process of reading data based on a first request from a host device. The memory controller is configured to, when the first request is received from the host device while causing the nonvolatile memory to execute a second process, hold interruption of the second process until a first number becomes a first threshold value or more. The first number is a number of the first requests to be performed in the memory controller. The first threshold value is an integer of 2 or more.

Patent Agency Ranking