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公开(公告)号：US20110231694A1
公开(公告)日：2011-09-22
申请号：US13152676
申请日：2011-06-03
Applicant: KAZUO SAKAMOTO , Naozumi Morino , Ikuo Kudo
Inventor： KAZUO SAKAMOTO , Naozumi Morino , Ikuo Kudo
IPC: G06F1/04
Abstract: A microcomputer is provided having a memory card interface capable of correctly latching data even when a card such as an MMC card is connected thereto. In the microcomputer having an interface with an external device such as a memory card, the interface unit is provided with an output driver connected to an external terminal for outputting a clock signal to output the clock signal and with an equivalent load circuit capable of imparting, to the clock signal extracted from an arbitrary position in a stage previous to the output driver in a clock signal path, delay equivalent to delay resulting from an external load connected to the external terminal in order to generate a clock signal for latching data inputted from the memory card.
Abstract translation: 即使当诸如MMC卡的卡连接到其上时，也提供具有能够正确地锁存数据的存储卡接口的微型计算机。 在具有与诸如存储卡的外部设备的接口的微型计算机中，接口单元设置有连接到外部端子的输出驱动器，用于输出时钟信号以输出时钟信号，并且具有能够传递时钟信号的等效负载电路， 与从时钟信号路径中的输出驱动器之前的级中的任意位置提取的时钟信号相当于连接到外部端子的外部负载引起的延迟的延迟，以便产生用于锁存从外部端子输入的数据的时钟信号 存储卡。
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公开(公告)号：US07490258B2
公开(公告)日：2009-02-10
申请号：US10827288
申请日：2004-04-20
Applicant: Kazuo Sakamoto , Naozumi Morino , Ikuo Kudo
Inventor： Kazuo Sakamoto , Naozumi Morino , Ikuo Kudo
Abstract: A microcomputer is provided having a memory card interface capable of correctly latching data even when a card such as an MMC card is connected thereto. In the microcomputer having an interface with an external device such as a memory card, the interface unit is provided with an output driver connected to an external terminal for outputting a clock signal to output the clock signal and with an equivalent load circuit capable of imparting, to the clock signal extracted from an arbitrary position in a stage previous to the output driver in a clock signal path, delay equivalent to delay resulting from an external load connected to the external terminal in order to generate a clock signal for latching data inputted from the memory card.
Abstract translation: 即使当诸如MMC卡的卡连接到其上时，也提供具有能够正确地锁存数据的存储卡接口的微型计算机。 在具有与诸如存储卡的外部设备的接口的微型计算机中，接口单元设置有连接到外部端子的输出驱动器，用于输出时钟信号以输出时钟信号，并且具有能够传递时钟信号的等效负载电路， 与从时钟信号路径中的输出驱动器之前的级中的任意位置提取的时钟信号相当于连接到外部端子的外部负载引起的延迟的延迟，以便产生用于锁存从外部端子输入的数据的时钟信号 存储卡。
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公开(公告)号：US08327180B2
公开(公告)日：2012-12-04
申请号：US13152676
申请日：2011-06-03
Applicant: Kazuo Sakamoto , Naozumi Morino , Ikuo Kudo
Inventor： Kazuo Sakamoto , Naozumi Morino , Ikuo Kudo
Abstract: A microcomputer is provided having a memory card interface capable of correctly latching data even when a card such as an MMC card is connected thereto. In the microcomputer having an interface with an external device such as a memory card, the interface unit is provided with an output driver connected to an external terminal for outputting a clock signal to output the clock signal and with an equivalent load circuit capable of imparting, to the clock signal extracted from an arbitrary position in a stage previous to the output driver in a clock signal path, delay equivalent to delay resulting from an external load connected to the external terminal in order to generate a clock signal for latching data inputted from the memory card.
Abstract translation: 即使当诸如MMC卡的卡连接到其上时，也提供具有能够正确地锁存数据的存储卡接口的微型计算机。 在具有与诸如存储卡的外部设备的接口的微型计算机中，接口单元设置有连接到外部端子的输出驱动器，用于输出时钟信号以输出时钟信号，并且具有能够传递时钟信号的等效负载电路， 与从时钟信号路径中的输出驱动器之前的级中的任意位置提取的时钟信号相当于连接到外部端子的外部负载引起的延迟的延迟，以便产生用于锁存从外部端子输入的数据的时钟信号 存储卡。
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公开(公告)号：US07966512B2
公开(公告)日：2011-06-21
申请号：US12348298
申请日：2009-01-04
Applicant: Kazuo Sakamoto , Naozumi Morino , Ikuo Kudo
Inventor： Kazuo Sakamoto , Naozumi Morino , Ikuo Kudo
Abstract: A microcomputer is provided having a memory card interface capable of correctly latching data even when a card such as an MMC card is connected thereto. In the microcomputer having an interface with an external device such as a memory card, the interface unit is provided with an output driver connected to an external terminal for outputting a clock signal to output the clock signal and with an equivalent load circuit capable of imparting, to the clock signal extracted from an arbitrary position in a stage previous to the output driver in a clock signal path, delay equivalent to delay resulting from an external load connected to the external terminal in order to generate a clock signal for latching data inputted from the memory card.
Abstract translation: 即使当诸如MMC卡的卡连接到其上时，也提供具有能够正确地锁存数据的存储卡接口的微型计算机。 在具有与诸如存储卡的外部设备的接口的微型计算机中，接口单元设置有连接到外部端子的输出驱动器，用于输出时钟信号以输出时钟信号，并且具有能够传递时钟信号的等效负载电路， 与从时钟信号路径中的输出驱动器之前的级中的任意位置提取的时钟信号相当于连接到外部端子的外部负载引起的延迟的延迟，以便产生用于锁存从外部端子输入的数据的时钟信号 存储卡。
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公开(公告)号：US08572425B2
公开(公告)日：2013-10-29
申请号：US13552693
申请日：2012-07-19
Applicant: Kazuo Sakamoto , Naozumi Morino , Ikuo Kudo
Inventor： Kazuo Sakamoto , Naozumi Morino , Ikuo Kudo
Abstract: A microcomputer is provided having a memory card interface capable of correctly latching data even when a card such as an MMC card is connected thereto. In the microcomputer having an interface with an external device such as a memory card, the interface unit is provided with an output driver connected to an external terminal for outputting a clock signal to output the clock signal and with an equivalent load circuit capable of imparting, to the clock signal extracted from an arbitrary position in a stage previous to the output driver in a clock signal path, delay equivalent to delay resulting from an external load connected to the external terminal in order to generate a clock signal for latching data inputted from the memory card.
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Patent Agency Ranking
公开(公告)号：US20090113231A1
公开(公告)日：2009-04-30
申请号：US12348298
申请日：2009-01-04
Applicant: Kazuo SAKAMOTO , Naozumi Morino , Ikuo Kudo
Inventor： Kazuo SAKAMOTO , Naozumi Morino , Ikuo Kudo
IPC: G06F1/04
Abstract: A microcomputer is provided having a memory card interface capable of correctly latching data even when a card such as an MMC card is connected thereto. In the microcomputer having an interface with an external device such as a memory card, the interface unit is provided with an output driver connected to an external terminal for outputting a clock signal to output the clock signal and with an equivalent load circuit capable of imparting, to the clock signal extracted from an arbitrary position in a stage previous to the output driver in a clock signal path, delay equivalent to delay resulting from an external load connected to the external terminal in order to generate a clock signal for latching data inputted from the memory card.
Abstract translation: 即使当诸如MMC卡的卡连接到其上时，也提供具有能够正确地锁存数据的存储卡接口的微型计算机。 在具有与诸如存储卡的外部设备的接口的微型计算机中，接口单元设置有连接到外部端子的输出驱动器，用于输出时钟信号以输出时钟信号，并且具有能够传递时钟信号的等效负载电路， 与从时钟信号路径中的输出驱动器之前的级中的任意位置提取的时钟信号相当于连接到外部端子的外部负载引起的延迟的延迟，以便产生用于锁存从外部端子输入的数据的时钟信号 存储卡。
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公开(公告)号：US20060180943A1
公开(公告)日：2006-08-17
申请号：US11401284
申请日：2006-04-11
Applicant: Takashi Miwa , Yasumi Tsutsumi , Masahiro Ichitani , Takanori Hashizume , Masamichi Sato , Naozumi Morino , Atsushi Nakamura , Saneaki Tamaki , Ikuo Kudo
Inventor： Takashi Miwa , Yasumi Tsutsumi , Masahiro Ichitani , Takanori Hashizume , Masamichi Sato , Naozumi Morino , Atsushi Nakamura , Saneaki Tamaki , Ikuo Kudo
CPC classification number: H01L25/0657 , H01L23/5386 , H01L25/18 , H01L2224/32145 , H01L2224/48091 , H01L2224/48227 , H01L2224/49171 , H01L2225/0651 , H01L2225/06527 , H01L2225/06541 , H01L2225/06555 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/00014 , H01L2924/00
Abstract: The present invention provides a semiconductor device having a stacked structure which realizes the miniaturization of a contour size and the reduction of thickness. The present invention also provides a semiconductor device which realizes high performance and high reliability in addition to the miniaturization of the contour size. The semiconductor device uses a package substrate on which bonding leads which are formed respectively corresponding to bonding pads for address and data which are distributed to opposing first and second sides of a memory chip and address terminals and data terminals which are connected to the bonding leads are formed. The semiconductor device further includes an address output circuit and a data input/output circuit which are also served for memory access and a signal processing circuit having a data processing function. A semiconductor chip in which bonding pads which are connected to the bonding leads corresponding to the address terminals of the package substrate and bonding pads which are connected to the bonding leads corresponding to the data terminals of the package substrate are distributed to two sides out of four sides and the above-mentioned memory chip are mounted on the package substrate in a stacked structure.
Abstract translation: 本发明提供一种具有层叠结构的半导体器件，其实现了轮廓尺寸的小型化和厚度的减小。 本发明还提供了除了轮廓尺寸的小型化之外还实现高性能和高可靠性的半导体器件。 半导体装置使用封装基板，在该封装基板上分别对应于分配给存储芯片的相对的第一和第二侧的地址和数据的接合焊盘形成的接合引线以及连接到接合引线的地址端子和数据端子 形成。 半导体器件还包括还用于存储器访问的地址输出电路和数据输入/输出电路以及具有数据处理功能的信号处理电路。 一种半导体芯片，其中连接到与封装基板的地址端子相对应的接合引线的接合焊盘和连接到与封装基板的数据端子对应的接合引线的接合焊盘分配到四个 侧面和上述存储芯片以堆叠结构安装在封装基板上。
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8.发明授权Stacked large-scale integrated circuit (LSI) semiconductor device with miniaturization and thinning of package 失效堆叠大型集成电路（LSI）半导体器件，封装小型化和薄型化公开(公告)号：US07061785B2
公开(公告)日：2006-06-13
申请号：US10606891
申请日：2003-06-27
Applicant: Takashi Miwa , Yasumi Tsutsumi , Masahiro Ichitani , Takanori Hashizume , Masamichi Sato , Naozumi Morino , Atsushi Nakamura , Saneaki Tamaki , Ikuo Kudo
Inventor： Takashi Miwa , Yasumi Tsutsumi , Masahiro Ichitani , Takanori Hashizume , Masamichi Sato , Naozumi Morino , Atsushi Nakamura , Saneaki Tamaki , Ikuo Kudo
IPC: G11C5/06
CPC classification number: H01L25/0657 , H01L23/5386 , H01L25/18 , H01L2224/32145 , H01L2224/48091 , H01L2224/48227 , H01L2224/49171 , H01L2225/0651 , H01L2225/06527 , H01L2225/06541 , H01L2225/06555 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/00014 , H01L2924/00
Abstract: A semiconductor device uses a package substrate on which bonding leads are formed respectively corresponding to bonding pads for address and data which are distributed to opposing first and second sides of a memory chip and address terminals and data terminals which are connected to the bonding leads. The semiconductor device further includes an address output circuit and a data input/output circuit which also serves for memory access and a signal processing circuit having a data processing function. A semiconductor chip having bonding pads connected to the bonding leads corresponding to the address terminals of the package substrate and bonding pads connected to the bonding leads corresponding to the data terminals of the package substrate and distributed to two sides out of four sides and the above-mentioned memory chip are mounted on the package substrate in a stacked structure.
Abstract translation: 半导体器件使用分别对应于分配到存储器芯片的相对的第一和第二侧的地址和数据的接合焊盘以及连接到接合引线的地址端子和数据端子分别形成有接合引线的封装基板。 半导体器件还包括地址输出电路和用于存储器访问的数据输入/输出电路和具有数据处理功能的信号处理电路。 一种半导体芯片，其具有连接到与封装基板的地址端子对应的接合引线的接合焊盘以及连接到与封装基板的数据端子相对应的接合引线的接合焊盘，并且分布在四边的两侧， 上述存储芯片以堆叠结构安装在封装基板上。
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公开(公告)号：US07286386B2
公开(公告)日：2007-10-23
申请号：US11401284
申请日：2006-04-11
Applicant: Takashi Miwa , Yasumi Tsutsumi , Masahiro Ichitani , Takanori Hashizume , Masamichi Sato , Naozumi Morino , Atsushi Nakamura , Saneaki Tamaki , Ikuo Kudo
Inventor： Takashi Miwa , Yasumi Tsutsumi , Masahiro Ichitani , Takanori Hashizume , Masamichi Sato , Naozumi Morino , Atsushi Nakamura , Saneaki Tamaki , Ikuo Kudo
CPC classification number: H01L25/0657 , H01L23/5386 , H01L25/18 , H01L2224/32145 , H01L2224/48091 , H01L2224/48227 , H01L2224/49171 , H01L2225/0651 , H01L2225/06527 , H01L2225/06541 , H01L2225/06555 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/00014 , H01L2924/00
Abstract: A semiconductor device uses a package substrate on which bonding leads are formed respectively corresponding to bonding pads for address and data which are distributed to opposing first and second sides of a memory chip and address terminals and data terminals which are connected to the bonding leads. The semiconductor device further includes an address output circuit and a data input/output circuit which also serves for memory access and a signal processing circuit having a data processing function. A semiconductor chip having bonding pads connected to the bonding leads corresponding to the address terminals of the package substrate and bonding pads connected to the bonding leads corresponding to the data terminals of the package substrate and distributed to two sides out of four sides and the above-mentioned memory chip are mounted on the package substrate in a stacked structure. Bonding leads arranged along at least one side of the substrate may include bonding leads of rectangular configuration having longer sides disposed at acute angles with respect to the side of the substrate.
Abstract translation: 半导体器件使用分别对应于分配到存储器芯片的相对的第一和第二侧的地址和数据的接合焊盘以及连接到接合引线的地址端子和数据端子分别形成有接合引线的封装基板。 半导体器件还包括地址输出电路和用于存储器访问的数据输入/输出电路和具有数据处理功能的信号处理电路。 一种半导体芯片，其具有连接到与封装基板的地址端子对应的接合引线的接合焊盘以及连接到与封装基板的数据端子相对应的接合引线的接合焊盘，并且分布在四边的两侧， 上述存储芯片以堆叠结构安装在封装基板上。 沿着衬底的至少一侧布置的接合引线可以包括具有相对于衬底的侧面以锐角设置的长边的矩形构造的接合引线。
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公开(公告)号：US07714357B2
公开(公告)日：2010-05-11
申请号：US12253850
申请日：2008-10-17
Applicant: Takahiro Hayashi , Shunsuke Toyoshima , Kazuo Sakamoto , Naozumi Morino , Kazuo Tanaka
Inventor： Takahiro Hayashi , Shunsuke Toyoshima , Kazuo Sakamoto , Naozumi Morino , Kazuo Tanaka
CPC classification number: H01L23/49844 , H01L23/49811 , H01L23/50 , H01L23/5226 , H01L23/5286 , H01L23/53228 , H01L23/585 , H01L24/05 , H01L24/06 , H01L24/49 , H01L27/0255 , H01L27/092 , H01L2224/02166 , H01L2224/05025 , H01L2224/05093 , H01L2224/05095 , H01L2224/05124 , H01L2224/05624 , H01L2224/06102 , H01L2224/06133 , H01L2224/06143 , H01L2224/06153 , H01L2224/06163 , H01L2224/49105 , H01L2224/85399 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/12036 , H01L2924/1306 , H01L2924/14 , H01L2924/00 , H01L2224/05599 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
Abstract: The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer.
Abstract translation: 本发明的目的是提供一种能够减小半导体器件的平面尺寸的技术。 在半导体衬底上形成输入/输出电路，接地布线和电源布线通过输入/输出电路，并且在其上形成用于焊盘的导电层。 输入/输出电路由nMISFET形成区域和pMISFET形成区域中的MISFET元件形成，电阻元件形成区域中的电阻元件和用作保护元件的二极管元件形成区域中的二极管元件。 连接到保护元件并位于接地布线和电源布线下方的布线在nMISFET形成区域和pMISFET形成区域之间以及接地布线和要连接的电源布线之间的拉出区域中拉出 到导电层。
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